Attention is currently required from: Patrick Rudolph, Deomid "rojer" Ryabkov.

Deomid "rojer" Ryabkov uploaded patch set #2 to this change.

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soc/intel/xeon_sp: Set the MRC "cold boot required" status bit

If bit 0 of byte 0x47 is set FSP will perform full memory training
even if previously saved data is supplied.

Up to and including FSP 2021 WW01 it was reset internally at the end
of PostMemoryInit. Starting with WW03 this is no longer the case and
Intel advised that this bit should be reset externally if valid MRC
data is present.

Change-Id: I9c4191d2fa2e0203b3464dcf40d845ede5f14c6b
Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
---
M 3rdparty/blobs
M 3rdparty/chromeec
M 3rdparty/fsp
M src/soc/intel/xeon_sp/cpx/chip.h
M src/soc/intel/xeon_sp/cpx/romstage.c
5 files changed, 21 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/51230/2

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