5 comments:
File src/device/pciexp_device.c:
These are just dummy index numbers and the resources will not be written to hardware? […]
This came from src/southbridge/intel/common/pciehp.c
Same question here with BAR1
This came from src/southbridge/intel/common/pciehp.c
Patch Set #2, Line 538: dummy->ops = &pciexp_hotplug_dummy_ops;
I like the dummy device approach, however it does make an additional reserve instead of guaranteeing […]
With Thunderbolt 3 currently coreboot does not set a security settings so it defaults to having no PCIe capability, meaning the bridges will not have any extra allocation by accident.
File src/include/device/device.h:
Patch Set #2, Line 133: /* hotplug buses to allocate */
Maybe better: Number of hotplug buses to allocate?
Done
File src/include/device/pciexp.h:
Patch Set #2, Line 29: #if CONFIG(PCIEXP_HOTPLUG)
No quard needed.
I think it is better to not declare the items inside this guard if they are not defined
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