Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Meera Ravindranath.

Deepti Deshatty uploaded patch set #6 to the change originally created by Meera Ravindranath.

View Change

mb/adlrvp: Fix DDR5 Boot issue

Currently, DDR5 boot is broken due to reading of spd data
via SMBus through coreboot. This implementation requires study
of spd5 architecture and is currently Work In Progress.
Switching to the older implemention of booting DDR5 by passing
DIMM slave address to FSP through this CL.

BUG=b:180458099
TEST=Boot DDR5 to kernel

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/6

To view, visit change 50996. To unsubscribe, or for help writing mail filters, visit settings.

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
Gerrit-Change-Number: 50996
Gerrit-PatchSet: 6
Gerrit-Owner: Meera Ravindranath <meera.ravindranath@intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@mailbox.org>
Gerrit-Attention: Furquan Shaikh <furquan@google.com>
Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Gerrit-Attention: Subrata Banik <subrata.banik@intel.com>
Gerrit-Attention: Meera Ravindranath <meera.ravindranath@intel.com>
Gerrit-MessageType: newpatchset