Terry Chen has uploaded this change for review.

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mb/google/volteer/variants/volteer2: Update DPTF parameters

1. Apply the DPTF parameters received from the thermal team.

BUG=b:169183507
TEST=build and verify by thermal tool

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I1a1a0f9e86e519ac15904fac80cf3c2299213e52
---
M src/mainboard/google/volteer/variants/volteer2/overridetree.cb
1 file changed, 74 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46087/1
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
index 0bb82f1..f9d54ca 100644
--- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
@@ -6,6 +6,80 @@
register "DdiPort2Hpd" = "0"

device domain 0 on
+ device pci 04.0 on
+ chip drivers/intel/dptf
+ ## Active Policy
+ register "policies.active" = "{
+ [3] = {.target = DPTF_TEMP_SENSOR_2,
+ .thresholds = {TEMP_PCT(53, 90),
+ TEMP_PCT(50, 69),
+ TEMP_PCT(48, 56),
+ TEMP_PCT(45, 46),
+ TEMP_PCT(42, 36),}},
+ [4] = {.target = DPTF_TEMP_SENSOR_3,
+ .thresholds = {TEMP_PCT(53, 90),
+ TEMP_PCT(50, 69),
+ TEMP_PCT(48, 56),
+ TEMP_PCT(45, 46),
+ TEMP_PCT(42, 36),}}}"
+ ## Passive Policy
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000),
+ [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000),
+ [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000),
+ [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}"
+
+ ## Critical Policy
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN),
+ [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN),
+ [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}"
+
+ ## Power Limits Control
+ # 10-15W PL1 in 200mW increments, avg over 28-32s interval
+ # PL2 is fixed at 64W, avg over 28-32s interval
+ register "controls.power_limits" = "{
+ .pl1 = {.min_power = 3000,
+ .max_power = 15000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 200,},
+ .pl2 = {.min_power = 15000,
+ .max_power = 60000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 1000,}}"
+
+ ## Charger Performance Control (Control, mA)
+ register "controls.charger_perf" = "{
+ [0] = { 255, 1700 },
+ [1] = { 24, 1500 },
+ [2] = { 16, 1000 },
+ [3] = { 8, 500 }}"
+
+ ## Fan Performance Control (Percent, Speed, Noise, Power)
+ register "controls.fan_perf" = "{
+ [0] = { 90, 6700, 220, 2200, },
+ [1] = { 80, 5800, 180, 1800, },
+ [2] = { 70, 5000, 145, 1450, },
+ [3] = { 60, 4900, 115, 1150, },
+ [4] = { 50, 3838, 90, 900, },
+ [5] = { 40, 2904, 55, 550, },
+ [6] = { 30, 2337, 30, 300, },
+ [7] = { 20, 1608, 15, 150, },
+ [8] = { 10, 800, 10, 100, },
+ [9] = { 0, 0, 0, 50, }}"
+
+ # Fan options
+ register "options.fan.fine_grained_control" = "1"
+ register "options.fan.step_size" = "2"
+
+ device generic 0 on end
+ end
+ end # DPTF 0x9A03
device pci 05.0 on end # IPU 0x9A19
device pci 15.0 on
chip drivers/i2c/generic

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1a1a0f9e86e519ac15904fac80cf3c2299213e52
Gerrit-Change-Number: 46087
Gerrit-PatchSet: 1
Gerrit-Owner: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Gerrit-MessageType: newchange