Xiang Wang uploaded patch set #6 to this change.

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riscv: workaround selfboot putting the coreboot table into prog_entry_arg

Change-Id: If6929897c7f12d8acb079eeebaef512ae506ca8b
Signed-off-by: Xiang Wang <wxjstz@126.com>
---
M src/arch/riscv/boot.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31477/6

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