Patrick Georgi submitted this change.

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Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
mb/google/deltaur: Update USB/WWAN config

Update USB3 ports configuration as schematics design.

BUG=b:155026295
TEST=Boot into OS and check WWAN device detected by lsusb.

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40818
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
index 498266e..e31c89b 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
@@ -48,6 +48,8 @@

register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2
+ register "usb3_ports[2]" = "USB3_PORT_EMPTY"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN

# PCIe root port 6 (WLAN), clock 1
register "PcieRpEnable[5]" = "1"
@@ -232,33 +234,21 @@
device usb 2.9 on end
end
chip drivers/usb/acpi
- register "desc" = ""Type-C Port 1""
- register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "desc" = ""Type-A Port 1""
+ register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device usb 3.0 on end
end
chip drivers/usb/acpi
- register "desc" = ""Type-C Port 2""
- register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "desc" = ""Type-A Port 2""
+ register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device usb 3.1 on end
end
chip drivers/usb/acpi
- register "desc" = ""Type-A Port 1 (Right)""
- register "type" = "UPC_TYPE_USB3_A"
- register "group" = "ACPI_PLD_GROUP(2, 2)"
- device usb 3.2 on end
- end
- chip drivers/usb/acpi
- register "desc" = ""Type-A Port 2 (Left)""
- register "type" = "UPC_TYPE_USB3_A"
- register "group" = "ACPI_PLD_GROUP(1, 2)"
- device usb 3.3 on end
- end
- chip drivers/usb/acpi
register "desc" = ""WWAN""
register "type" = "UPC_TYPE_INTERNAL"
- device usb 3.4 on end
+ device usb 3.2 on end
end
end
end
@@ -297,7 +287,7 @@
device pci 1c.0 on end # PCIe Root Port #1 (USB)
device pci 1c.1 on end # PCIe Root Port #2 (USB)
device pci 1c.2 off end # PCIe Root Port #3 ()
- device pci 1c.3 on end # PCIe Root Port #4 (WWAN)
+ device pci 1c.3 off end # PCIe Root Port #4 (WWAN)
device pci 1c.4 on end # PCIe Root Port #5 (LTE)
device pci 1c.5 on end # PCIe Root Port #6 (WiFi)
device pci 1c.6 on end # PCIe Root Port #7 (Card reader)

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf
Gerrit-Change-Number: 40818
Gerrit-PatchSet: 3
Gerrit-Owner: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com>
Gerrit-Reviewer: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Selma Bensaid <selma.bensaid@intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: merged