Attention is currently required from: Lean Sheng Tan.
Werner Zeh has uploaded this change for review.
soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher
Depending on the real workload that is executed on the system the L1
prefetcher might be too aggressive and will populate the L1 cache ahead
with data that is not really needed. This will in the end result in a
higher cache miss rate thus slowing down the real application.
This patch provides a devicetree option to disable the L1 prefetcher if
needed. This can be requested on mainboard level if needed.
Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
---
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/cpu.c
2 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/68667/1
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index d63844f..94a2cdf 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -454,6 +454,9 @@
* 3600, 3733, 4000, 4200, 4267 and 0 for Auto.
*/
uint16_t max_dram_speed_mts;
+
+ /* Disable L1 prefetcher */
+ bool L1_prefetcher_disable;
};
typedef struct soc_intel_elkhartlake_config config_t;
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c
index f4baa65..8ba28c0 100644
--- a/src/soc/intel/elkhartlake/cpu.c
+++ b/src/soc/intel/elkhartlake/cpu.c
@@ -67,6 +67,14 @@
msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */
msr.lo |= (1 << 23); /* Lock it */
wrmsr(MSR_POWER_CTL, msr);
+
+ /* In some cases it is beneficial for the performance to disable the
+ L1 prefetcher as on Elkhart Lake it is set up a bit too aggressive. */
+ if (conf->L1_prefetcher_disable) {
+ msr = rdmsr(MSR_PREFETCH_CTL);
+ msr.lo |= PREFETCH_L1_DISABLE;
+ wrmsr(MSR_PREFETCH_CTL, msr);
+ }
}
/* All CPUs including BSP will run the following function. */
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