PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/22819
Change subject: soc/intel/skylake: Enable LPC IO Decoding on PCR ......................................................................
soc/intel/skylake: Enable LPC IO Decoding on PCR
According to the PCH BIOS Spec (Doc#549921/Rev-2.3.4), section 2.5.1.6, it is a requirement to program the same value programmed in LPC "PCI offset 82h" into "PCR[DMI]+2774h" to fully enable the Lpc IO enable decoding which is missing in current source.
Without above changes, Skylake Saddlebrook platform with using SIO does not able to boot.
Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173 Signed-off-by: praveen praveenx.hodagatta.pranesh@intel.com --- M src/soc/intel/skylake/lpc.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/22819/1
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index bd6fbc4..b5105e4 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -31,6 +31,7 @@ #include <reg_script.h> #include <soc/iomap.h> #include <soc/pcr_ids.h> +#include <soc/intel/common/block/lpc/lpc_def.h>
/** PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF @@ -81,11 +82,17 @@
void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) { + uint16_t lpc_en; + /* Mirror these same settings in DMI PCR */ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); + + /* LPC IO Decode Enable */ + lpc_en = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en); }
static const struct reg_script pch_misc_init_script[] = {