Attention is currently required from: Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50723 )
Change subject: cpu/intel/pre-haswell: Don't initialize SMM on BSP early ......................................................................
cpu/intel/pre-haswell: Don't initialize SMM on BSP early
Initializing SMM on the BSP early is only useful when relocation via MSRs is possible. This hardware does not support those MSRs.
TESTED: asus/p5ql-em boots and SMM is relocated on CPU 0.
Change-Id: I42068249061bcf40ee34ed7fd25791e565a4d07c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/smm/gen1/smmrelocate.c 4 files changed, 6 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/50723/1
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index fd6a82a..fec3532 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -37,11 +37,6 @@
/* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL to enable SMRR so configure IA32_FEATURE_CONTROL early on */ -static void pre_mp_smm_init(void) -{ - smm_initialize(); -} - #define SMRR_SUPPORTED (1 << 11)
static void per_cpu_smm_trigger(void) @@ -71,7 +66,7 @@ }
/* Relocate the SMM handler. */ - smm_relocate(); + smm_initiate_relocation(); }
static void post_mp_init(void) @@ -89,7 +84,7 @@ .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = pre_mp_smm_init, + .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index dd2aeef..a373ecf 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -154,7 +154,7 @@ static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ - smm_relocate(); + smm_initiate_relocation();
/* After SMM relocation a 2nd microcode load is required. */ const void *microcode_patch = intel_microcode_find(); @@ -176,7 +176,7 @@ .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, + .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index beb885e..bc311f9 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -420,7 +420,7 @@ static void per_cpu_smm_trigger(void) { /* Relocate the SMM handler. */ - smm_relocate(); + smm_initiate_relocation();
/* After SMM relocation a 2nd microcode load is required. */ const void *microcode_patch = intel_microcode_find(); @@ -442,7 +442,7 @@ .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = smm_initialize, + .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 8dffceb..5d8bf66a 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -140,18 +140,6 @@ *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); }
-void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); -} - /* The relocation work is actually performed in SMM context, but the code * resides in the ramstage module. This occurs by trampolining from the default * SMRAM entry point to here. */ @@ -194,22 +182,3 @@ else write_smrr(relo_params); } - -/* - * The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. - */ -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do the final move. For APs, a relocation handler always - * needs to be run. - */ - if (!boot_cpu()) - smm_initiate_relocation(); -}