Patrick Rudolph has uploaded this change for review.
[WIP]soc/intel/apollolake: Select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Use common mpinit code as GLK does. Drop now dead code path.
Change-Id: Ibdc5468fdd86f88bc8a09a69bfbc59279d1e3828
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/include/soc/cpu.h
4 files changed, 3 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/49313/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 62049b5..0f8846f 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -1,5 +1,6 @@
config SOC_INTEL_APOLLOLAKE
bool
+ select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
help
Intel Apollolake support
@@ -8,7 +9,6 @@
default n
select SOC_INTEL_APOLLOLAKE
select SOC_INTEL_COMMON_BLOCK_CNVI
- select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_SGX
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select IDT_IN_EVERY_STAGE
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 9670a31..ac4924d 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -202,20 +202,11 @@
.acpi_name = &soc_acpi_name,
};
-static struct device_operations cpu_bus_ops = {
- .read_resources = noop_read_resources,
- .set_resources = noop_set_resources,
- .init = apollolake_init_cpus,
- .acpi_fill_ssdt = generate_cpu_entries,
-};
-
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
- dev->ops = &cpu_bus_ops;
else if (dev->path.type == DEVICE_PATH_GPIO)
block_gpio_enable(dev);
}
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 0ae170b..7d0cf8a 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -83,32 +83,6 @@
}
}
-#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
-static void soc_init_core(struct device *cpu)
-{
- soc_core_init(cpu);
-}
-
-static struct device_operations cpu_dev_ops = {
- .init = soc_init_core,
-};
-
-static const struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },
- { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },
- { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 },
- { X86_VENDOR_INTEL, CPUID_GLK_A0 },
- { X86_VENDOR_INTEL, CPUID_GLK_B0 },
- { X86_VENDOR_INTEL, CPUID_GLK_R0 },
- { 0, 0 },
-};
-
-static const struct cpu_driver driver __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
-#endif
-
/*
* MP and SMM loading initialization.
*/
@@ -123,7 +97,6 @@
/*
* Do essential initialization tasks before APs can be fired up.
*
- * IF (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) -
* Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP,
* that are set prior to ramstage.
* Real MTRRs are programmed after resource allocation.
@@ -132,56 +105,12 @@
* external stage cache in TSEG does not flush off due to SMM relocation
* during MP Init stage.
*
- * ELSE -
- * Enable MTRRs on the BSP. This creates the MTRR solution that the
- * APs will use. Otherwise APs will try to apply the incomplete solution
- * as the BSP is calculating it.
*/
static void pre_mp_init(void)
{
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) {
- fsps_load(romstage_handoff_is_resume());
- return;
- }
- x86_setup_mtrrs_with_detect();
- x86_mtrr_check();
-
- /* Enable the local CPU apics */
- setup_lapic();
+ fsps_load(romstage_handoff_is_resume());
}
-#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
-static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
-{
- msr_t msr;
- msr = rdmsr(MSR_CORE_THREAD_COUNT);
- *num_virt = (msr.lo >> 0) & 0xffff;
- *num_phys = (msr.lo >> 16) & 0xffff;
-}
-
-/* Find CPU topology */
-int get_cpu_count(void)
-{
- unsigned int num_virt_cores, num_phys_cores;
-
- read_cpu_topology(&num_phys_cores, &num_virt_cores);
-
- printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n",
- num_phys_cores, num_virt_cores);
-
- return num_virt_cores;
-}
-
-void get_microcode_info(const void **microcode, int *parallel)
-{
- *microcode = intel_microcode_find();
- *parallel = 1;
-
- /* Make sure BSP is using the microcode from cbfs */
- intel_microcode_load_unlocked(*microcode);
-}
-#endif
-
static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
@@ -253,16 +182,4 @@
/* Clear for take-off */
if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n");
-}
-
-void apollolake_init_cpus(struct device *dev)
-{
- if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT))
- return;
- soc_init_cpus(dev->link_list);
-
- /* Temporarily cache the memory-mapped boot media. */
- if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) &&
- CONFIG(BOOT_DEVICE_SPI_FLASH))
- fast_spi_cache_bios_region();
-}
+}
\ No newline at end of file
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 38b830a..55eb6b2 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -7,7 +7,6 @@
#include <intelblocks/msr.h>
struct device;
-void apollolake_init_cpus(struct device *dev);
void mainboard_devtree_update(struct device *dev);
/* Flush L1D to L2 */
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