8 comments:
File src/soc/qualcomm/sc7180/display/dsi_phy.c:
Patch Set #32, Line 39: static struct dsi_phy_divider_lut_entry_type pll_dividerlut_dphy[] = {
If there's an assumption that pll_post_div must always be a power of 2, that should be documented he […]
Done
Patch Set #32, Line 79: uint32_t escape_freq;
unused?
Done
Patch Set #32, Line 622: for (i = 0; i < 4; i++) {
I think you can replace this loop with just log2(pll_cfg->pll_post_div)?
Done
Patch Set #32, Line 739: while (i < ARRAY_SIZE(clks)) {
nit: This should really use for, not while.
Done
File src/soc/qualcomm/sc7180/display/dsi_phy.c:
Patch Set #33, Line 606: vco_freq_hz = pll_output_freq_hz * pll_post_div;
Why are you calculating this when the caller only checks the result for 0? Might as well leave out t […]
Done
File src/soc/qualcomm/sc7180/display/dsi_phy_pll.c:
Patch Set #32, Line 21: u32 pll_lockdet_rate;
unused?
Done
Patch Set #32, Line 93: regs->pll_prop_gain_rate = 12;
Where is this used?
it should be used here : dsi_pll_config_hzindep_reg(). Updated
Should this maybe not be hardcoded?
Done
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