[coreboot-gerrit] Change in coreboot[master]: soc/intel/{apl,glk}: add options to configure GPU

[Maxim Polyakov (Code Review)]

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39374 )

Change subject: soc/intel/{apl,glk}: add options to configure GPU
......................................................................

soc/intel/{apl,glk}: add options to configure GPU

Adds options to select the primary GPU device and configure IGD, which
allows to override the appropriate FSP options in the SoC code. These
changes do not affect the configuration of the boards with the Apollo
Lake and Gemini Lake processors, because if these parameters are not
defined in the devicetree, they will be set to the default values.

Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c
Signed-off-by: Maxim Polyakov 
---
M src/soc/intel/apollolake/chip.h
M src/soc/intel/apollolake/romstage.c
2 files changed, 64 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39374/1

diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 40cd39b..0375cec 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -44,6 +44,46 @@
    /* Common structure containing soc config data required by common code*/
    struct soc_intel_common_config common_soc_config;

+	/* Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size */
+	enum {
+		DVMT_64MB = 2, /* Default */
+		DVMT_96MB,
+		DVMT_128MB,
+		DVMT_160MB,
+		DVMT_192MB,
+		DVMT_224MB,
+		DVMT_256MB,
+		DVMT_288MB,
+		DVMT_320MB,
+		DVMT_352MB,
+		DVMT_384MB,
+		DVMT_416MB,
+		DVMT_448MB,
+		DVMT_480MB,
+		DVMT_512MB,
+	} igd_dvmt_50_pre_alloc_size;
+
+	/* Select the Aperture Size for GPU device */
+	enum {
+		APERTURE_128MB = 1, /* Default */
+		APERTURE_256MB,
+		APERTURE_512MB,
+	} igd_aperture_size;
+
+	/* Select the GTT Size for GPU device */
+	enum {
+		GTT_2MB = 1,
+		GTT_4MB,
+		GTT_8MB, /* Default */
+	} igd_gtt_size;
+
+	/* Select primary GPU device */
+	enum {
+		PRIMARY_AUTO = 0, /* Default */
+		PRIMARY_IGD  = 2,
+		PRIMARY_PCI  = 3,
+	} primary_gpu;
+
    /*
     * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
     * four CLKREQ inputs, but six root ports. Root ports without an
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 05cd0db..1576802 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -264,12 +264,34 @@
    }
 }

+static void soc_gpu_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	const struct soc_intel_apollolake_config *soc_cfg = config_of_soc();
+	const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
+
+	m_cfg->PrimaryVideoAdaptor = soc_cfg->primary_gpu;
+	if (dev && dev->enabled && (soc_cfg->primary_gpu != PRIMARY_PCI)) {
+		/*
+		 * Override FSP settings for IGD only if they are set in the devicetree.
+		 * Otherwise, the default values from UPD will be used for them
+		 */
+		if (soc_cfg->igd_dvmt_50_pre_alloc_size)
+			m_cfg->IgdDvmt50PreAlloc = soc_cfg->igd_dvmt_50_pre_alloc_size;
+
+		if (soc_cfg->igd_aperture_size)
+			m_cfg->IgdApertureSize = soc_cfg->igd_aperture_size;
+
+		if (soc_cfg->igd_gtt_size)
+			m_cfg->GttSize = soc_cfg->igd_gtt_size;
+	}
+}
+
 static void soc_memory_init_params(FSPM_UPD *mupd)
 {
 #if CONFIG(SOC_INTEL_GLK)
    /* Only for GLK */
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-
    m_cfg->PrmrrSize = get_prmrr_size();

/*
@@ -307,6 +329,7 @@
    check_full_retrain(mupd);

fill_console_params(mupd);
+	soc_gpu_init_params(mupd);

if (CONFIG(SOC_INTEL_GLK))
    	soc_memory_init_params(mupd);