EricR Lai has uploaded this change for review.
mb/google/drallion: dynamic disable memory channel
Disable memory channel by HW strap pin. Using for factory
debug. Keep this until the real board come out.
BUG=b:139773082
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e
---
M src/mainboard/google/drallion/romstage.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35241/1
diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c
index 20eee7f..6e62a1e 100644
--- a/src/mainboard/google/drallion/romstage.c
+++ b/src/mainboard/google/drallion/romstage.c
@@ -16,6 +16,8 @@
#include <ec/google/wilco/romstage.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
+#include <gpio.h>
+#include <variant/gpio.h>
static const struct cnl_mb_cfg memcfg = {
/* Access memory info through SMBUS. */
@@ -59,5 +61,9 @@
{
wilco_ec_romstage_init();
+ /* Disable memory channel by HW strap pin */
+ memupd->FspmConfig.DisableDimmChannel0 = gpio_get(GPP_F1)? 0 : 3;
+ memupd->FspmConfig.DisableDimmChannel1 = gpio_get(GPP_F2)? 0 : 3;
+
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}
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