Attention is currently required from: Paul Menzel, Yu-Ping Wu.

Jianjun Wang uploaded patch set #13 to this change.

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soc/mediatek: Enable PCIe support for mt8195

Enable PCIe support for mt8195.

TEST=Build pass and boot up to kernel successfully via SSD on Cherry
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x1987
PCI SSVID : 0x1987
SN : 28F40713077B0012602
MN : Phison ESE1A043-X28
RAB : 0x1
AERL : 0x3
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model Phison ESE1A043-X28

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff
---
M src/soc/mediatek/mt8195/Kconfig
M src/soc/mediatek/mt8195/soc.c
2 files changed, 14 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/56793/13

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff
Gerrit-Change-Number: 56793
Gerrit-PatchSet: 13
Gerrit-Owner: Jianjun Wang <jianjun.wang@mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte@chromium.org>
Gerrit-Reviewer: Yu-Ping Wu <yupingso@google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Arthur Heymans <arthur.heymans@9elements.com>
Gerrit-CC: Paul Menzel <paulepanter@mailbox.org>
Gerrit-Attention: Paul Menzel <paulepanter@mailbox.org>
Gerrit-Attention: Yu-Ping Wu <yupingso@google.com>
Gerrit-MessageType: newpatchset