Patrick Georgi submitted this change.
sb/intel/i82801gx: Use symbolic name for register, code rework
An original code had a wrong register address 0x27 for AHCI BAR.
The value was aligned incidentally by the code specific of
the pci_read_config32 function to the correct address 0x24.
All 0x24 values in sata.c were changed to the symbolic name
PCI_BASE_ADDRESS_5 and the code was optimized.
An equivalent code was tested on a real hardware.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35737
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/southbridge/intel/i82801gx/sata.c
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 24dbf7c..47c35ba 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -94,7 +94,6 @@
{
u32 reg32;
u16 reg16;
- u32 *ahci_bar;
u8 ports;
/* Get the chip configuration */
@@ -117,7 +116,7 @@
case SATA_MODE_IDE_LEGACY_COMBINED:
printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
/* No AHCI: clear AHCI base */
- pci_write_config32(dev, 0x24, 0x00000000);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
/* And without AHCI BAR no memory decoding */
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
@@ -155,8 +154,11 @@
/* Interrupt Pin is set by D31IP.PIP */
pci_write_config8(dev, INTR_LN, 0x0a);
- ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
- ahci_bar[3] = config->sata_ports_implemented;
+ struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5);
+ if (ahci_res != NULL)
+ /* write AHCI GHC_PI register */
+ write32(res2mmio(ahci_res, 0xc, 0),
+ config->sata_ports_implemented);
break;
default:
case SATA_MODE_IDE_PLAIN:
@@ -165,7 +167,7 @@
pci_write_config8(dev, SATA_MAP, 0x00);
/* No AHCI: clear AHCI base */
- pci_write_config32(dev, 0x24, 0x00000000);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
/* And without AHCI BAR no memory decoding */
reg16 = pci_read_config16(dev, PCI_COMMAND);
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