HAOUAS Elyes has uploaded this change for review.
nb/intel/haswell: Use common MCHBAR accessor functions
This change the binary using "BUILD_TIMELESS=1" for lenovo/t440p baord.
Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/cpu/intel/haswell/haswell_init.c
M src/northbridge/intel/haswell/Makefile.inc
M src/northbridge/intel/haswell/acpi.c
M src/northbridge/intel/haswell/early_init.c
M src/northbridge/intel/haswell/finalize.c
M src/northbridge/intel/haswell/haswell.h
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/raminit.c
8 files changed, 19 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/1
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 5f3debb..86c69f8 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -14,6 +14,7 @@
#include <cpu/intel/turbo.h>
#include <cpu/x86/name.h>
#include <delay.h>
+#include <northbridge/intel/common/mchbar_ops.h>
#include <northbridge/intel/haswell/haswell.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <cpu/intel/common/common.h>
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index b2fd530..8f9f33d 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -11,14 +11,17 @@
ramstage-y += acpi.c
ramstage-y += minihd.c
+ramstage-y += ../common/mchbar_ops.c
romstage-y += memmap.c
romstage-y += raminit.c
romstage-y += romstage.c
romstage-y += early_init.c
romstage-y += report_platform.c
+romstage-y += ../common/mchbar_ops.c
smm-y += finalize.c
+smm-y += ../common/mchbar_ops.c
# We don't ship that, but booting without it is bound to fail
cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index cc4487c..81ed757 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -7,6 +7,7 @@
#include <device/device.h>
#include <device/pci_ops.h>
#include "haswell.h"
+#include <northbridge/intel/common/mchbar_ops.h>
#include <southbridge/intel/lynxpoint/pch.h>
unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 9db6a9d..b1fe430 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -5,6 +5,7 @@
#include <device/mmio.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
+#include <northbridge/intel/common/mchbar_ops.h>
#include "haswell.h"
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c
index 93c89ce..ebce6e9 100644
--- a/src/northbridge/intel/haswell/finalize.c
+++ b/src/northbridge/intel/haswell/finalize.c
@@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_ops.h>
+#include <northbridge/intel/common/mchbar_ops.h>
+
#include "haswell.h"
void intel_northbridge_haswell_finalize_smm(void)
@@ -17,13 +19,13 @@
pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */
pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */
- MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */
- MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */
- MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */
- MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
- MCHBAR32_OR(REQLIM, 1UL << 31);
- MCHBAR32_OR(DMIVCLIM, 1UL << 31);
- MCHBAR32_OR(CRDTLCK, 1 << 0);
+ mchbar32_set(MMIO_PAVP_MSG, 1 << 0); /* PAVP */
+ mchbar32_set(SAPMCTL, 1UL << 31); /* SA PM */
+ mchbar32_set(UMAGFXCTL, 1 << 0); /* UMA GFX */
+ mchbar32_set(VTDTRKLCK, 1 << 0); /* VTDTRK */
+ mchbar32_set(REQLIM, 1UL << 31);
+ mchbar32_set(DMIVCLIM, 1UL << 31);
+ mchbar32_set(CRDTLCK, 1 << 0);
/* Memory Controller Lockdown */
MCHBAR8(MC_LOCK) = 0x8f;
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 44ea9b9..5cacec6 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -27,22 +27,8 @@
/*
* MCHBAR
+ * As there are many registers, define them on a separate file
*/
-
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
-#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
-#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
-#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or))
-#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or))
-#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or))
-#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or))
-#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or))
-#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
-
-/* As there are many registers, define them on a separate file */
#include "registers/mchbar.h"
#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index e1c26d1..fd4a238 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -12,6 +12,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <boot/tables.h>
+#include <northbridge/intel/common/mchbar_ops.h>
#include "chip.h"
#include "haswell.h"
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 9c6c00f..f382db5 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -16,6 +16,8 @@
#include <spd.h>
#include <security/vboot/vboot_common.h>
#include <commonlib/region.h>
+#include <northbridge/intel/common/mchbar_ops.h>
+
#include "raminit.h"
#include "pei_data.h"
#include "haswell.h"
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