Felix Held has uploaded this change for review.
soc/amd/cezanne: add SMU support
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5b9b4c3d57945ea7c3287cf47f3d9704f42ff24b
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.inc
A src/soc/amd/cezanne/include/soc/smu.h
A src/soc/amd/cezanne/smu.c
4 files changed, 45 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/51233/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 4a308df..d491da4 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -42,6 +42,7 @@
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_SMM
+ select SOC_AMD_COMMON_BLOCK_SMU
select SOC_AMD_COMMON_BLOCK_SPI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_UART
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 35e7009..16b69f3 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -37,6 +37,7 @@
ramstage-y += uart.c
smm-y += smihandler.c
+smm-y += smu.c
smm-$(CONFIG_DEBUG_SMI) += uart.c
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
diff --git a/src/soc/amd/cezanne/include/soc/smu.h b/src/soc/amd/cezanne/include/soc/smu.h
new file mode 100644
index 0000000..560c9e4
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/smu.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_SMU_H
+#define AMD_CEZANNE_SMU_H
+
+/*
+ * SMU mailbox register offsets in indirect address space accessed by an index/data pair in
+ * D0F00 config space.
+ */
+#define REG_ADDR_MESG_ID 0x3b10528
+#define REG_ADDR_MESG_RESP 0x3b10564
+#define REG_ADDR_MESG_ARGS_BASE 0x3b10998
+
+#define SMU_NUM_ARGS 6
+
+enum smu_message_id {
+ SMC_MSG_S3ENTRY = 0x0b,
+};
+
+/*
+ * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines S-State and
+ * SlpTypeEn gets set by the SMU. Function does not return if successful.
+ */
+void smu_sx_entry(void);
+
+#endif /* AMD_CEZANNE_SMU_H */
diff --git a/src/soc/amd/cezanne/smu.c b/src/soc/amd/cezanne/smu.c
new file mode 100644
index 0000000..1496957
--- /dev/null
+++ b/src/soc/amd/cezanne/smu.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <amdblocks/smu.h>
+#include <soc/smu.h>
+
+/*
+ * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and
+ * SlpTypeEn gets set by the SMU. Function does not return if successful.
+ */
+void smu_sx_entry(void)
+{
+ struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */
+
+ printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n");
+ send_smu_message(SMC_MSG_S3ENTRY, &msg);
+}
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