awokd@danwin1210.me uploaded patch set #2 to this change.

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vc/amd/agesa: Fix out of bounds read

ByteLane is incorrectly used unitialized from prior for statement.
Found nothing in following code that attempted to reference
PassTestRxEnDly at that index, so appears safe to delete.
Additionally, found nothing following with the
OutOfRange[ByteLane]==TRUE condition that would expect
'PassTestRxEnDly[ByteLane] = RxOrig[ByteLane];'.

Change-Id: Icd18a146aba6b6120d37518d8c40c7efbc05afa3
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241804
---
M src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c
M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c
3 files changed, 0 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36192/2

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