Jamie Ryu uploaded patch set #8 to this change.

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mb/intel/tglrvp: Enable HECI interface

This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.
PAVP feature is enabled with CSE Lite SKU for Chrome and HECI1 interface
is required between kernel and CSE Lite.

BUG=None
TEST=Build and boot tglrvp. Run lspci and check pcie device
00:16.0 Communication controller: Intel Corporation Device a0e0

Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/42307/8

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705
Gerrit-Change-Number: 42307
Gerrit-PatchSet: 8
Gerrit-Owner: Jamie Ryu <jamie.m.ryu@intel.com>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu@intel.com>
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Gerrit-Reviewer: Raj Astekar <raj.astekar@intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
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