Christian Walter has uploaded this change for review.
util/inteltool: Add Kabylake E3-1200 MSRs
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad
---
M util/inteltool/cpu.c
1 file changed, 349 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32619/1
diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index c40a3bd..e985df7 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -1529,6 +1529,354 @@
{ 0x416, "MSR_MC5_ADDR" },
};
+/*
+ * Intel 64 and IA-32 Architectures Software Developers Manual Conbined Volumes
+ * Page 4668
+ *
+ * The following two tables are for the Kaby Lake processors
+ * 06_9EH.
+ *
+ */
+
+ static const msr_entry_t model96ex_global_msrs[] = {
+ { 0x0000, "IA32_PLATFORM_ID"},
+ { 0x0080, "MSR_TRACE_HUB_STH_ACPIBAR_BASE"},
+ { 0x00CE, "MSR_PLATFORM_INFO"},
+ { 0x0198, "IA32_PERF_STATUS"},
+ { 0x01A2, "MSR_TEMPERATURE_TARGET"},
+ { 0x01AD, "MSR_TURBO_RATIO_LIMIT"},
+ { 0x0180, "IA32_ENERGY_PERF_BIAS"},
+ { 0x0181, "IA32_PACKAGE_THERM_STATUS"},
+ { 0x0182, "IA32_PACKAGE_THERM_INTERRUPT"},
+ { 0x0284, "IA32_MC4_CTL2"},
+ { 0x02F4, "MSR_UNCORE_PRMRR_PHYS_BASE"},
+ { 0x02F5, "MSR_UNCORE_PRMRR_PHYS_MASK"},
+ { 0x0300, "MSR_SFXOWNEREPOCH0"},
+ { 0x0301, "MSR_SGXOWNEREPOCH1"},
+ { 0x0394, "MSR_UNC_PERF_FIXED_CTRL"},
+ { 0x0395, "MSR_UNC_PERF_FIXED_CTR"},
+ /*{ 0x03F8, "MSR_PKG_C3_RESIDENCY"},
+ { 0x03F9, "MSR_PKG_C6_RESIDENCY"},
+ { 0x03FA, "MSR_PKG_C7_RESIDENCY"},
+ { 0x0606, "MSR_RAPL_POWER_UNIT"}, */
+ { 0x060A, "MSR_PKGC3_IRTL"},
+ { 0x060B, "MSR_PKGC6_IRTL"},
+ { 0x060D, "MSR_PKG_C2_RESIDENCY"},
+ { 0x0610, "MSR_PKG_POWER_LIMIT"},
+ { 0x0614, "MSR_PKG_POWER_INFO"},
+ { 0x0620, "MSR_RING_RATIO_LIMIT"},
+ { 0x0638, "MSR_PP0_POWER_LIMIT"},
+ /*{ 0x0639, "MSR_PKG_ENERGY_STATUS"},
+ { 0x064D, "MSR_PLATFORM_ENERGY_COUNTER"}*/
+ { 0x064F, "MSR_CORE_PERF_LIMIT_REASONS"},
+ { 0x0652, "MSR_PKG_HDC_CONFIG"},
+ /*{ 0x0653, "MSR_CORE_HDC_RESIDENCY"},
+ { 0x0655, "MSR_PKG_HDC_SHALLOW_RESIDENCY"},
+ { 0x0656, "MSR_PKG_HDC_DEEP_RESIDENCY"},
+ { 0x0658, "MSR_WEIGHTED_CORE_C0"},
+ { 0x0659, "MSR_ANY_CORE_C0"},
+ { 0x065A, "MSR_ANY_GFXE_C0"},
+ { 0x065B, "MSR_CORE_GFXE_OVERLAP_C0"}, */
+ { 0x065C, "MSR_PLATFORM_POWER_LIMIT"},
+ { 0x06B0, "MSR_GRAPHICS_PERF_LIMIT_REASONS"},
+ { 0x06B1, "MSR_RING_PERF_LIMIT_REASONS"},
+ { 0x0770, "IA32_PM_ENABLE"},
+ { 0x0772, "IA32_HWP_REQUEST_PKG"},
+ { 0x0DB0, "IA32_PKG_HDC_CTL"},
+ { 0x03B0, "MSR_UNC_ARB_PERFCTR0"},
+ { 0x03B1, "MSR_UNC_ARB_PERFCTR1"},
+ { 0x03B2, "MSR_UNC_ARB_PERFEVTSEL0"},
+ { 0x03B3, "MSR_UNC_ARB_PERFEVTSEL1"},
+ { 0x0700, "MSR_UNC_CBO_0_PERFCTR0"},
+ { 0x0701, "MSR_UNC_CBO_0_PERFCTR1"},
+ { 0x0706, "MSR_UNC_CBO_0_PERFEVTSEL0"},
+ { 0x0707, "MSR_UNC_CBO_0_PERFEVTSEL1"},
+ { 0x0710, "MSR_UNC_CBO_1_PERFCTR0"},
+ { 0x0711, "MSR_UNC_CBO_1_PERFCTR1"},
+ { 0x0716, "MSR_UNC_CBO_1_PERFEVTSEL0"},
+ { 0x0717, "MSR_UNC_CBO_1_PERFEVTSEL1"},
+ { 0x0720, "MSR_UNC_CBO_2_PERFCTR0"},
+ { 0x0721, "MSR_UNC_CBO_2_PERFCTR1"},
+ { 0x0726, "MSR_UNC_CBO_2_PERFEVTSEL0"},
+ { 0x0727, "MSR_UNC_CBO_2_PERFEVTSEL1"},
+ { 0x0730, "MSR_UNC_CBO_3_PERFCTR0"},
+ { 0x0731, "MSR_UNC_CBO_3_PERFCTR1"},
+ { 0x0736, "MSR_UNC_CBO_3_PERFEVTSEL0"},
+ { 0x0737, "MSR_UNC_CBO_3_PERFEVTSEL1"},
+ { 0x0E01, "MSR_UNC_PERF_GLOBAL_CTRL"},
+ { 0x0E02, "MSR_UNC_PERF_GLOBAL_STATUS"},
+ };
+
+ static const msr_entry_t model96ex_per_core_msrs[] = {
+ /* Per core MSRs for Sandy Bridge and above */
+ { 0x0000, "IA32_P5_MC_ADDR"},
+ { 0x0001, "IA32_P5_MC_TYPE"},
+ { 0x0006, "IA32_MONITOR_FILTER_SIZE"},
+ { 0x0010, "IA32_TIME_STAMP_COUNTER"},
+ { 0x0018, "IA32_APIC_BASE"},
+ { 0x0034, "MSR_SMI_COUNT"},
+ { 0x003A, "IA32_FEATURE_CONTROL"},
+ { 0x008B, "IA32_BIOS_SIGN_ID"},
+ { 0x00C1, "IA32_PMC0" },
+ { 0x00C2, "IA32_PMC1" },
+ { 0x00C3, "IA32_PMC2" },
+ { 0x00C4, "IA32_PMC3" },
+ { 0x00C5, "IA32_PMC4" },
+ { 0x00C6, "IA32_PMC5" },
+ { 0x00C7, "IA32_PMC6" },
+ { 0x00C8, "IA32_PMC7" },
+ { 0x00E2, "MSR_PKG_CST_CONFIG_CONTROL" },
+ { 0x00E4, "MSR_PMG_IO_CAPTURE_BASE"},
+ { 0x00E7, "IA32_MPERF"},
+ { 0x00E8, "IA32_APERF"},
+ { 0x00FE, "IA32_MTRRCAP"},
+ { 0x013C, "MSR_FEATURE_CONFIG"},
+ { 0x0174, "IA32_SYSENTER_CS"},
+ { 0x0175, "IA32_SYSENTER_ESP"},
+ { 0x0176, "IA32_SYSENTER_EIP"},
+ { 0x0179, "IA32_MCG_CAP"},
+ { 0x017A, "IA32_MCG_STATUS"},
+ { 0x0186, "IA32_PERFEVTSEL0"},
+ { 0x0187, "IA32_PERFEVTSEL1"},
+ { 0x0188, "IA32_PERFEVTSEL2"},
+ { 0x0189, "IA32_PERFEVTSEL3"},
+ { 0x018A, "IA32_PERFEVTSEL4"},
+ { 0x018B, "IA32_PERFEVTSEL5"},
+ { 0x018C, "IA32_PERFEVTSEL6"},
+ { 0x018D, "IA32_PERFEVTSEL7"},
+ { 0x0199, "IA32_PERF_CTL"},
+ { 0x019A, "IA32_CLOCK_MODULATION"},
+ { 0x019B, "IA32_THERM_INTERRUPT"},
+ { 0x019C, "IA32_THERM_STATUS"},
+ { 0x01A0, "IA32_MISC_ENABLE"},
+ { 0x01A4, "IA32_MISC_FEATURE_CONTROL"},
+ { 0x01A6, "MSR_OFFCORE_RSP_0"},
+ { 0x01A7, "MSR_OFFCORE_RSP_1"},
+ { 0x01C8, "MSR_LBR_SELECT"},
+ { 0x01C9, "MSR_LASTBRANCH_TOS"},
+ { 0x01D9, "IA32_DEBUGCTL"},
+ { 0x01DD, "MSR_LER_FROM_LIP"},
+ { 0x01DE, "MSR_LER_TO_LIP"},
+ { 0x01F2, "IA32_SMRR_PHYSBASE"},
+ { 0x01F3, "IA32_SMRR_PHYSMASK"},
+ { 0x01F4, "MSR_PRMRR_PHYS_BASE"},
+ { 0x01F5, "MSR_PRMRR_PHYS_MASK"},
+ { 0x01F4, "MSR_PRMRR_PHYS_BASE"},
+ { 0x01FB, "MSR_PRMRR_VALID_CONFIG"},
+ { 0x01FC, "MSR_POWER_CTL"},
+ { 0x0200, "IA32_MTRR_PHYSBASE0"},
+ { 0x0201, "IA32_MTRR_PHYSBASE0"},
+ { 0x0202, "IA32_MTRR_PHYSBASE1"},
+ { 0x0203, "IA32_MTRR_PHYSBASE1"},
+ { 0x0204, "IA32_MTRR_PHYSBASE2"},
+ { 0x0205, "IA32_MTRR_PHYSBASE2"},
+ { 0x0206, "IA32_MTRR_PHYSBASE3"},
+ { 0x0207, "IA32_MTRR_PHYSBASE3"},
+ { 0x0208, "IA32_MTRR_PHYSBASE4"},
+ { 0x0209, "IA32_MTRR_PHYSBASE4"},
+ { 0x020A, "IA32_MTRR_PHYSBASE5"},
+ { 0x020B, "IA32_MTRR_PHYSBASE5"},
+ { 0x020C, "IA32_MTRR_PHYSBASE6"},
+ { 0x020D, "IA32_MTRR_PHYSBASE6"},
+ { 0x020E, "IA32_MTRR_PHYSBASE7"},
+ { 0x020F, "IA32_MTRR_PHYSBASE7"},
+ { 0x0210, "IA32_MTRR_PHYSBASE8"},
+ { 0x0211, "IA32_MTRR_PHYSBASE8"},
+ { 0x0212, "IA32_MTRR_PHYSBASE9"},
+ { 0x0213, "IA32_MTRR_PHYSBASE9"},
+ { 0x0250, "IA32_MTRR_FIX64K_00000"},
+ { 0x0258, "IA32_MTRR_FIX16K_80000"},
+ { 0x0259, "IA32_MTRR_FIX16K_A0000"},
+ { 0x0268, "IA32_MTRR_FIX4K_C0000"},
+ { 0x0269, "IA32_MTRR_FIX4K_C8000"},
+ { 0x026A, "IA32_MTRR_FIX4K_D0000"},
+ { 0x026B, "IA32_MTRR_FIX4K_D8000"},
+ { 0x026C, "IA32_MTRR_FIX4K_E0000"},
+ { 0x026D, "IA32_MTRR_FIX4K_E8000"},
+ { 0x026E, "IA32_MTRR_FIX4K_F0000"},
+ { 0x026F, "IA32_MTRR_FIX4K_F8000"},
+ { 0x0277, "IA32_PAT"},
+ { 0x0280, "IA32_MC0_CTL2"},
+ { 0x0281, "IA32_MC1_CTL2"},
+ { 0x0282, "IA32_MC2_CTL2"},
+ { 0x0283, "IA32_MC3_CTL2"},
+ { 0x02FF, "IA32_MTRR_DEF_TYPE"},
+ { 0x0309, "IA32_FIXED_CTR0"},
+ { 0x030A, "IA32_FIXED_CTR1"},
+ { 0x030B, "IA32_FIXED_CTR2"},
+ { 0x0345, "IA32_PERF_CAPABILITIES"},
+ { 0x038D, "IA32_FIXED_CTR_CTRL"},
+ { 0x038E, "IA32_PERF_GLOBAL_STATUS"},
+ { 0x038F, "IA32_PERF_GLOBAL_CTRL"},
+ { 0x0390, "IA32_PERF_GLOBAL_STATUS_RESET"},
+ { 0x0391, "IA32_PERF_GLOBAL_STATUS_SET"},
+ { 0x03F1, "MSR_PEBS_ENABLE"},
+ { 0x03F6, "MSR_PEBS_LD_LAT"},
+ { 0x03F7, "MSR_PEBS_FRONTEND"},
+ { 0x03FC, "MSR_CORE_C3_RESIDENCY"},
+ { 0x03FD, "MSR_CORE_C6_RESIDENCY"},
+ { 0x03FE, "MSR_CORE_C7_RESIDENCY"},
+ { 0x0400, "IA32_MC0_CTL" },
+ { 0x0401, "IA32_MC0_STATUS" },
+ { 0x0402, "IA32_MC0_ADDR" },
+ { 0x0403, "IA32_MC0_MISC" },
+ { 0x0404, "IA32_MC1_CTL" },
+ { 0x0405, "IA32_MC1_STATUS" },
+ { 0x0406, "IA32_MC1_ADDR" },
+ { 0x0407, "IA32_MC1_MISC" },
+ { 0x0408, "IA32_MC2_CTL" },
+ { 0x0409, "IA32_MC2_STATUS" },
+ { 0x040a, "IA32_MC2_ADDR" },
+ { 0x040c, "IA32_MC3_CTL" },
+ { 0x040d, "IA32_MC3_STATUS" },
+ { 0x040e, "IA32_MC3_ADDR" },
+ { 0x0410, "IA32_MC4_CTL" },
+ { 0x0411, "IA32_MC4_STATUS" },
+ { 0x0480, "IA32_VMX_BASIC" },
+ { 0x0481, "IA32_VMX_PINBASED_CTLS" },
+ { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
+ { 0x0483, "IA32_VMX_EXIT_CTLS" },
+ { 0x0484, "IA32_VMX_ENTRY_CTLS" },
+ { 0x0485, "IA32_VMX_MISC" },
+ { 0x0486, "IA32_VMX_CR0_FIXED0" },
+ { 0x0487, "IA32_VMX_CR0_FIXED1" },
+ { 0x0488, "IA32_VMX_CR4_FIXED0" },
+ { 0x0489, "IA32_VMX_CR4_FIXED1" },
+ { 0x048a, "IA32_VMX_VMCS_ENUM" },
+ { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
+ { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
+ { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
+ { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
+ { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
+ { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
+ { 0x04C1, "IA32_A_PMC0"},
+ { 0x04C2, "IA32_A_PMC1"},
+ { 0x04C3, "IA32_A_PMC2"},
+ { 0x04C4, "IA32_A_PMC3"},
+ { 0x04C5, "IA32_A_PMC4"},
+ { 0x04C6, "IA32_A_PMC5"},
+ { 0x04C7, "IA32_A_PMC6"},
+ { 0x04C8, "IA32_A_PMC7"},
+ { 0x0500, "IA32_SGX_SVN_STATUS"},
+ { 0x0560, "IA32_RTIT_OUTPUT_BASE"},
+ { 0x0561, "IA32_RTIT_OUTPUT_MASK_PTRS"},
+ { 0x0570, "IA32_RTIT_CTL"},
+ { 0x0571, "IA32_RTIT_STATUS"},
+ { 0x0572, "IA32_RTIT_CR3_MATCH"},
+ { 0x0580, "IA32_RTIT_ADDR0_A"},
+ { 0x0581, "IA32_RTIT_ADDR0_B"},
+ { 0x0582, "IA32_RTIT_ADDR1_A"},
+ { 0x0583, "IA32_RTIT_ADDR1_B"},
+ { 0x0600, "IA32_DS_AREA" },
+ { 0x064E, "MSR_PPERF"},
+ { 0x0653, "MSR_CORE_HDC_RESIDENCY"},
+ { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" },
+ { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" },
+ { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" },
+ { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" },
+ { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" },
+ { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" },
+ { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" },
+ { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" },
+ { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" },
+ { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" },
+ { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" },
+ { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" },
+ { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" },
+ { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" },
+ { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" },
+ { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" },
+ { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" },
+ { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" },
+ { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" },
+ { 0x0693, "MSR_LASTBRANCH_19_FROM_IP" },
+ { 0x0694, "MSR_LASTBRANCH_20_FROM_IP" },
+ { 0x0695, "MSR_LASTBRANCH_21_FROM_IP" },
+ { 0x0696, "MSR_LASTBRANCH_22_FROM_IP" },
+ { 0x0697, "MSR_LASTBRANCH_23_FROM_IP" },
+ { 0x0698, "MSR_LASTBRANCH_24_FROM_IP" },
+ { 0x0699, "MSR_LASTBRANCH_25_FROM_IP" },
+ { 0x069A, "MSR_LASTBRANCH_26_FROM_IP" },
+ { 0x069B, "MSR_LASTBRANCH_27_FROM_IP" },
+ { 0x069C, "MSR_LASTBRANCH_28_FROM_IP" },
+ { 0x069D, "MSR_LASTBRANCH_29_FROM_IP" },
+ { 0x069E, "MSR_LASTBRANCH_30_FROM_IP" },
+ { 0x069F, "MSR_LASTBRANCH_31_FROM_IP" },
+ { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" },
+ { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" },
+ { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" },
+ { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" },
+ { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" },
+ { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" },
+ { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" },
+ { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" },
+ { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" },
+ { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" },
+ { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" },
+ { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" },
+ { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" },
+ { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" },
+ { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" },
+ { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" },
+ { 0x06d0, "MSR_LASTBRANCH_16_FROM_IP" },
+ { 0x06d1, "MSR_LASTBRANCH_17_FROM_IP" },
+ { 0x06d2, "MSR_LASTBRANCH_18_FROM_IP" },
+ { 0x06d3, "MSR_LASTBRANCH_19_FROM_IP" },
+ { 0x06d4, "MSR_LASTBRANCH_20_FROM_IP" },
+ { 0x06d5, "MSR_LASTBRANCH_21_FROM_IP" },
+ { 0x06d6, "MSR_LASTBRANCH_22_FROM_IP" },
+ { 0x06d7, "MSR_LASTBRANCH_23_FROM_IP" },
+ { 0x06d8, "MSR_LASTBRANCH_24_FROM_IP" },
+ { 0x06d9, "MSR_LASTBRANCH_25_FROM_IP" },
+ { 0x06da, "MSR_LASTBRANCH_26_FROM_IP" },
+ { 0x06db, "MSR_LASTBRANCH_27_FROM_IP" },
+ { 0x06dc, "MSR_LASTBRANCH_28_FROM_IP" },
+ { 0x06dd, "MSR_LASTBRANCH_29_FROM_IP" },
+ { 0x06de, "MSR_LASTBRANCH_30_FROM_IP" },
+ { 0x06df, "MSR_LASTBRANCH_31_FROM_IP" },
+ { 0x06E0, "IA32_TSC_DEADLINE"},
+ { 0x0771, "IA32_HWP_CAPABILITIES"},
+ { 0x0773, "IA32_HWP_INTERRUPT"},
+ { 0x0774, "IA32_HWP_REQUEST"},
+ { 0x0777, "IA32_HWP_STATUS"},
+ { 0x0D90, "IA32_BNDCFGS"},
+ { 0x0DA0, "IA32_XSS"},
+ { 0x0DB1, "IA32_PM_CTL1"},
+ { 0x0DB2, "IA32_THREAD_STALL"},
+ { 0x0DC0, "IA32_LBR_INFO_0"},
+ { 0x0DC1, "IA32_LBR_INFO_1"},
+ { 0x0DC2, "IA32_LBR_INFO_2"},
+ { 0x0DC3, "IA32_LBR_INFO_3"},
+ { 0x0DC4, "IA32_LBR_INFO_4"},
+ { 0x0DC5, "IA32_LBR_INFO_5"},
+ { 0x0DC6, "IA32_LBR_INFO_6"},
+ { 0x0DC7, "IA32_LBR_INFO_7"},
+ { 0x0DC8, "IA32_LBR_INFO_8"},
+ { 0x0DC9, "IA32_LBR_INFO_9"},
+ { 0x0DCA, "IA32_LBR_INFO_10"},
+ { 0x0DCB, "IA32_LBR_INFO_11"},
+ { 0x0DCC, "IA32_LBR_INFO_12"},
+ { 0x0DCD, "IA32_LBR_INFO_13"},
+ { 0x0DCE, "IA32_LBR_INFO_14"},
+ { 0x0DCF, "IA32_LBR_INFO_15"},
+ { 0x0DD0, "IA32_LBR_INFO_16"},
+ { 0x0DD1, "IA32_LBR_INFO_17"},
+ { 0x0DD2, "IA32_LBR_INFO_18"},
+ { 0x0DD3, "IA32_LBR_INFO_19"},
+ { 0x0DD4, "IA32_LBR_INFO_20"},
+ { 0x0DD5, "IA32_LBR_INFO_21"},
+ { 0x0DD6, "IA32_LBR_INFO_22"},
+ { 0x0DD7, "IA32_LBR_INFO_23"},
+ { 0x0DD8, "IA32_LBR_INFO_24"},
+ { 0x0DD9, "IA32_LBR_INFO_25"},
+ { 0x0DDA, "IA32_LBR_INFO_26"},
+ { 0x0DDB, "IA32_LBR_INFO_27"},
+ { 0x0DDC, "IA32_LBR_INFO_28"},
+ { 0x0DDD, "IA32_LBR_INFO_29"},
+ { 0x0DDE, "IA32_LBR_INFO_30"},
+ { 0x0DDF, "IA32_LBR_INFO_31"},
+ };
+
typedef struct {
unsigned int model;
const msr_entry_t *global_msrs;
@@ -1547,6 +1895,7 @@
{ 0x00f60, modelf6x_global_msrs, ARRAY_SIZE(modelf6x_global_msrs), modelf6x_per_core_msrs, ARRAY_SIZE(modelf6x_per_core_msrs) },
{ 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
{ 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) },
+ { 0x906e0, model96ex_global_msrs, ARRAY_SIZE(model96ex_global_msrs), model96ex_per_core_msrs, ARRAY_SIZE(model96ex_per_core_msrs) },
{ CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */
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