2 comments:
File src/cpu/intel/smm/gen1/smmrelocate.c:
I'd not remove this check. If this is not the case, I recall there were some weird issues. […]
If setup is wrong, is worth coming to ramstage at all? Fail even before postcar, because stage cache would attempt to access TSEG earlier.
File src/northbridge/intel/gm45/memmap.c:
Patch Set #1, Line 140: sub_size
ASSERT(sub_size > cache_size) somewhere?
Ack
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