Abhay Kumar (abhay.kumar@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14575
-gerrit
commit c98419a429b15a051a8457bb181edcaac285c01e Author: Abhay Kumar abhay.kumar@intel.com Date: Sat Apr 30 13:57:47 2016 -0700
intel/amenia: Remove PEIM GFX from normal mode and S3 resume.
Change-Id: I9da58eb17111e8c47fffcf7fec96f02c111bdb16 Signed-off-by: Abhay Kumar abhay.kumar@intel.com --- src/soc/intel/apollolake/chip.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 6e0a90f..177949c 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -29,6 +29,7 @@ #include <soc/cpu.h> #include <soc/nvs.h> #include <soc/pci_devs.h> +#include <vendorcode/google/chromeos/chromeos.h>
#include "chip.h"
@@ -83,8 +84,12 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; static struct soc_intel_apollolake_config *cfg;
- /* Load VBT before devicetree-specific config. */ - silconfig->GraphicsConfigPtr = fsp_load_vbt(); + /* Load VBT before devicetree-specific config but not in Normal mode + and S3 resume */ + if (developer_mode_enabled() || recovery_mode_enabled()) { + silconfig->GraphicsConfigPtr = fsp_load_vbt(); + }else + silconfig->GraphicsConfigPtr = (uintptr_t)NULL;
struct device *dev = NB_DEV_ROOT; if (!dev || !dev->chip_info) {