Arthur Heymans has uploaded this change for review.

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cpu/intel/common: Compute the TSC tick freq based on FSB

This allows the cbmem utility to compute timestamps based on coreboot
tables without relying on other userspace components.

Change-Id: Ie87adec950dc51f4f873c0d852a325b3ff9b18bf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/cpu/intel/common/fsb.c
1 file changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31203/1

diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
index 1f7c391..cf258bd 100644
--- a/src/cpu/intel/common/fsb.c
+++ b/src/cpu/intel/common/fsb.c
@@ -11,7 +11,9 @@
  * GNU General Public License for more details.
  */
 
+#include <console/console.h>
 #include <cpu/cpu.h>
+#include <cpu/x86/tsc.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/fsb.h>
@@ -83,3 +85,27 @@
 	printk(BIOS_ERR, "FSB not supported or not found\n");
 	return -1;
 }
+
+unsigned long tsc_freq_mhz(void)
+{
+	msr_t msr;
+	unsigned long multiplier;
+	struct cpuinfo_x86 c;
+
+	get_fms(&c, cpuid_eax(1));
+
+	msr = rdmsr(IA32_PLATFORM_ID);
+	multiplier = (msr.lo & SPEEDSTEP_RATIO_VALUE_MASK)
+		>> SPEEDSTEP_RATIO_SHIFT;
+	if ((c.x86 == 6 && c.x86_model == 0xe) || (c.x86 == 0xf)) {
+		/* Looks like Yonah CPUs don't have the frequency ratio in
+		   IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading
+		   should be reliable as those CPUs don't have turbo mode. */
+		msr = rdmsr(IA32_PERF_STATUS);
+		multiplier = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK)
+			>> SPEEDSTEP_RATIO_SHIFT;
+	}
+
+	printk(BIOS_DEBUG, "CPU freq %ld\n", multiplier * get_ia32_fsb());
+	return multiplier * get_ia32_fsb();
+}

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