Patrick Georgi merged this change.
nb/intel/gm45: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Lenovo thinkpad X200: on cold boot the external stage cache
gets created and the cached ramstage gets successfully used on the S3
resume path.
Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25604
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/Makefile.inc
A src/northbridge/intel/gm45/stage_cache.c
3 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index ef6b4ef..f1318eb 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -30,6 +30,7 @@
select POSTCAR_CONSOLE
select SMM_TSEG
select PARALLEL_MP
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config CBFS_SIZE
hex
@@ -47,4 +48,8 @@
hex
default 0xf0000000
+config SMM_RESERVED_SIZE
+ hex
+ default 0x100000
+
endif
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index c12bbf1..95b360c 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -38,4 +38,8 @@
postcar-y += ram_calc.c
+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+
endif
diff --git a/src/northbridge/intel/gm45/stage_cache.c b/src/northbridge/intel/gm45/stage_cache.c
new file mode 100644
index 0000000..ed3b9d4
--- /dev/null
+++ b/src/northbridge/intel/gm45/stage_cache.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <device/pci.h>
+#include <stage_cache.h>
+#include <cpu/intel/smm/gen1/smi.h>
+#include "gm45.h"
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+ /*
+ * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ * The top of RAM is defined to be the TSEG base address.
+ */
+ *size = CONFIG_SMM_RESERVED_SIZE;
+ *base = (void *)(northbridge_get_tseg_base()
+ + CONFIG_SMM_RESERVED_SIZE);
+}
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