[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add required FSP UPD changes for CML

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31284 )

Change subject: soc/intel/cannonlake: Add required FSP UPD changes for CML
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Patch Set 5:

(4 comments)

https://review.coreboot.org/#/c/31284/5/src/soc/intel/cannonlake/chip.h 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/#/c/31284/5/src/soc/intel/cannonlake/chip.h@39 
PS5, Line 39: SOC_INTEL_UART_DEV_MAX
SOC_INTEL_CML_UART_DEV_MAX?

https://review.coreboot.org/#/c/31284/5/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/31284/5/src/soc/intel/cannonlake/fsp_params.... 
PS5, Line 39: params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
Just use memcpy?

https://review.coreboot.org/#/c/31284/5/src/soc/intel/cannonlake/fsp_params.... 
PS5, Line 42: params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
same here?

https://review.coreboot.org/#/c/31284/5/src/soc/intel/cannonlake/fsp_params.... 
PS5, Line 45: params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
same here.