[coreboot-gerrit] [XS] Change in coreboot[main]: src/soc/intel/braswell/Kconfig: Correct CONFIG_DCACHE_RAM_SIZE

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82256?usp=email )

Change subject: src/soc/intel/braswell/Kconfig: Correct CONFIG_DCACHE_RAM_SIZE
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src/soc/intel/braswell/Kconfig: Correct CONFIG_DCACHE_RAM_SIZE

In log warning ´Wrong CAR region used'is reported.
Configured size is 0x8000 where FSP-T is returning value 0x4000.

Set CONFIG_CACHE_RAM_SIZE to 0x4000

BUG = N/A
TEST = Built and boot facebook fbg1701 and verify log file

Change-Id: Ieb781d5f0645a75cce0dc7a3808b2af3e3ce245a
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/82256/1

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index d9bb481..24cf68a 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -93,7 +93,7 @@

config DCACHE_RAM_SIZE
    hex
-	default 0x8000
+	default 0x4000
    help
      The size of the cache-as-ram region required during bootblock
      and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE