Martin Roth has uploaded this change for review.

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WIP: Backlight enable patches.

The change in smihandler.c shouldn't be needed, but the ACPI didn't seem
to be doing the trick. Matt's looking into this.

BUG=b:184198808
TEST=Backlight enabled in the OS

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c
---
M src/mainboard/google/guybrush/mainboard.c
M src/mainboard/google/guybrush/smihandler.c
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
3 files changed, 65 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/52113/1
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c
index 57f658c..3ad03a4 100644
--- a/src/mainboard/google/guybrush/mainboard.c
+++ b/src/mainboard/google/guybrush/mainboard.c
@@ -1,13 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
#include <amdblocks/amd_pci_util.h>
#include <baseboard/variants.h>
#include <device/device.h>
+#include <gpio.h>
#include <soc/acpi.h>
#include <variant/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>

-/*
+#define BACKLIGHT_GPIO GPIO_129
+#define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN"
+#define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS"
+#define METHOD_MAINBOARD_INI "\\_SB.MINI"
+#define METHOD_MAINBOARD_WAK "\\_SB.MWAK"
+#define METHOD_MAINBOARD_PTS "\\_SB.MPTS"
+
+/***********************************************************
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
* This table is responsible for physically routing the PIC and
* IOAPIC IRQs to the different PCI devices on the system. It
@@ -104,15 +114,62 @@
mainboard_ec_init();
}

+static void mainboard_write_blken(void)
+{
+ acpigen_write_method(METHOD_BACKLIGHT_ENABLE, 0);
+ acpigen_soc_clear_tx_gpio(BACKLIGHT_GPIO);
+ acpigen_pop_len();
+}
+
+static void mainboard_write_blkdis(void)
+{
+ acpigen_write_method(METHOD_BACKLIGHT_DISABLE, 0);
+ acpigen_soc_set_tx_gpio(BACKLIGHT_GPIO);
+ acpigen_pop_len();
+}
+
+static void mainboard_write_mini(void)
+{
+ acpigen_write_method(METHOD_MAINBOARD_INI, 0);
+ acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE);
+ acpigen_pop_len();
+}
+
+static void mainboard_write_mwak(void)
+{
+ acpigen_write_method(METHOD_MAINBOARD_WAK, 0);
+ acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE);
+ acpigen_pop_len();
+}
+
+static void mainboard_write_mpts(void)
+{
+ acpigen_write_method(METHOD_MAINBOARD_PTS, 0);
+ acpigen_emit_namestring(METHOD_BACKLIGHT_DISABLE);
+ acpigen_pop_len();
+}
+
+static void mainboard_fill_ssdt(const struct device *dev)
+{
+ mainboard_write_blken();
+ mainboard_write_blkdis();
+ mainboard_write_mini();
+ mainboard_write_mpts();
+ mainboard_write_mwak();
+}
+
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");

dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
+ dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;

init_tables();
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
+
+
}

struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/guybrush/smihandler.c b/src/mainboard/google/guybrush/smihandler.c
index 6facb76..e1138fc 100644
--- a/src/mainboard/google/guybrush/smihandler.c
+++ b/src/mainboard/google/guybrush/smihandler.c
@@ -4,6 +4,7 @@
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
+#include <gpio.h>
#include <elog.h>
#include <variant/ec.h>

@@ -27,6 +28,11 @@
{
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);

+ /* Temporary fix - Needs to go into ACPI instead */
+ /* Turn on the backlight when we go to ACPI mode */
+ if (apmc == APM_CNT_ACPI_ENABLE)
+ gpio_set(GPIO_129, 0);
+
return 0;
}

diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 719590f..ddd7ee3 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -137,7 +137,7 @@
PAD_GPO(GPIO_121, LOW),
/* GPIO_122 - GPIO_128: Not available */
/* SOC_DISABLE_DISP_BL */
- PAD_GPO(GPIO_129, LOW),
+ PAD_GPO(GPIO_129, HIGH),
/* WLAN_DISABLE */
PAD_GPO(GPIO_130, HIGH),
/* CLK_REQ3_L */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c
Gerrit-Change-Number: 52113
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth@google.com>
Gerrit-MessageType: newchange