Hannah Williams (hannah.williams@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15055
-gerrit
commit ae6dad1b8a9af2c5668eca6b76c96f968a3c31de Author: Saurabh Satija saurabh.satija@intel.com Date: Tue May 3 15:15:31 2016 -0700
soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree
Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784 Signed-off-by: Saurabh Satija saurabh.satija@intel.com Signed-off-by: Hannah Williams hannah.williams@intel.com --- src/soc/intel/apollolake/chip.c | 2 ++ src/soc/intel/apollolake/chip.h | 3 +++ 2 files changed, 5 insertions(+)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 044ef91..edf4a56 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -255,6 +255,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
+ silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; + /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0; } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..0cde7d7 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -79,6 +79,9 @@ struct soc_intel_apollolake_config {
/* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + + /* Configure LPSS S0ix Enable */ + uint8_t lpss_s0ix_enable; };
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */