[coreboot-gerrit] [M] Change in coreboot[master]: src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic

[Cliff Huang (Code Review)]

Attention is currently required from: Bora Guvendik, Hannah Williams, Anil Kumar K, Cliff Huang, Jérémy Compostella.

Hello Bora Guvendik, build bot (Jenkins), Hannah Williams, Anil Kumar K, Jérémy Compostella, Eric Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/72826

to look at the new patch set (#3).

Change subject: src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic
......................................................................

src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic

_ON() calls _STA() at the beginning. If _STA() indicates the device is
ON, it exits immediately. Before exiting, it needs to check if it was
scheduled to be skipped first.

NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following
by a device reset such as WWAN device. When such device calls its
_RST(), it increments OFSK. When the following _OFF() is called, it
was scheduled to skip, it will aslo increments ONSK. Similarly, when
the following _ON() is called, it checks if the previous _OFF was
skipped or not. If skipped, it needs to do the same. In normal
suspend/resume cases, these two variables remains '0'. No _OFF() and
 _ON() calls are skipped.

entire generated code:

Method (_ON, 0, Serialized)  // _ON_: Power On
{
    Local0 = _SB.PCI0.RP01.RTD3._STA ()
    If ((Local0 == One))
    {
        If ((ONSK > Zero))
        {
            ONSK--
        }

Return (One)
    }

If ((ONSK == Zero))
    {
        Acquire (_SB.PCI0.R3MX, 0xFFFF)
        EMPG = Zero
        Local7 = 0x06
        While ((Local7 > Zero))
        {
            If ((AMPG == Zero))
            {
                Break
            }

Sleep (0x10)
            Local7--
        }

Release (_SB.PCI0.R3MX)
        _SB.PCI0.PMC.IPCS (0xAC, Zero, 0x10, 0x00000020, 0x00000020,
          0x00000020, 0x00000020)
        _SB.PCI0.STXS (0x015E)
        If ((NCB7 == One))
        {
            L23R = One
            Local7 = 0x14
            While ((Local7 > Zero))
            {
                If ((L23R == Zero))
                {
                    Break
                }

Sleep (0x10)
                Local7--
            }

NCB7 = Zero
            Local7 = 0x08
            While ((Local7 > Zero))
            {
                If ((LASX == One))
                {
                    Break
                }

Sleep (0x10)
                Local7--
            }
        }
    }
    Else
    {
        ONSK--
    }
}

BUG=b:241850118
TEST=Use above functions and check the generated SSDT table after OS
boot.

Signed-off-by: Cliff Huang 
Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62
---
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
1 file changed, 103 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/72826/3