Way too many stoney or stoneyridge. I hope I found them all.
108 comments:
File src/soc/amd/picasso/BiosCallOuts.c:
Patch Set #2, Line 63: STONEYRIDGE
PICASSO
Patch Set #2, Line 70: STONEYRIDGE
PICASSO
Patch Set #2, Line 72: STONEYRIDGE
PICASSO
Patch Set #2, Line 102: stoneyridge
picasso
File src/soc/amd/picasso/Kconfig:
config SOC_AMD_STONEYRIDGE_FP4
bool
help
AMD Stoney Ridge FP4 support
config SOC_AMD_STONEYRIDGE_FT4
bool
help
AMD Stoney Ridge FT4 support
if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
PICASSO, how many sockets will it support?
Patch Set #2, Line 145: stoneyridge
picasso
Patch Set #2, Line 159: STONEYRIDGE
PICASSO
Patch Set #2, Line 160: Stoney Ridge
Picasso
Patch Set #2, Line 169: STONEYRIDGE
PICASSO
Patch Set #2, Line 173: Stoney Ridge
Picasso
Patch Set #2, Line 175: STONEYRIDGE
PICASSO
Patch Set #2, Line 179: Stoney Ridge
Picasso
Patch Set #2, Line 182: STONEYRIDGE
PICASSO
Patch Set #2, Line 184: stoneyridge
picasso
Patch Set #2, Line 185: STONEYRIDGE
PICASSO
Patch Set #2, Line 187: STONEYRIDGE
PICASSO
Patch Set #2, Line 189: STONEYRIDGE
PICASSO
Patch Set #2, Line 193: stoneyridge
picasso
Patch Set #2, Line 195: TONEYRIDGE
PICASSO
Patch Set #2, Line 211: TONEYRIDGE
PICASSO
Patch Set #2, Line 214: STONEYRIDGE
PICASSO
Patch Set #2, Line 217: STONEYRIDGE
PICASSO
Patch Set #2, Line 220: STONEYRIDGE
PICASSO
Patch Set #2, Line 223: STONEYRIDGE
PICASSO
Patch Set #2, Line 226: STONEYRIDGE
PICASSO
Patch Set #2, Line 228: if STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
PICASSO, 2 places
default "1022,7801" if STONEYRIDGE_SATA_MODE = 2
default "1022,7804" if STONEYRIDGE_SATA_MODE = 5
endif # STONEYRIDGE_SATA_MODE = 2 || STONEYRIDGE_SATA_MODE = 5
config STONEYRIDGE_LEGACY_FREE
PICASSO
Patch Set #2, Line 250: TONEYRIDGE
PICASSO
Patch Set #2, Line 257: STONEYRIDGE
PICASSO
Patch Set #2, Line 389: SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
PICASSO, how many sockets?
File src/soc/amd/picasso/acpi.c:
Patch Set #2, Line 78: STONEYRIDGE
PICASSO
File src/soc/amd/picasso/acpi/globalnvs.asl:
Patch Set #2, Line 20: stoneyridg
picasso
File src/soc/amd/picasso/bootblock/bootblock.c:
Patch Set #2, Line 111: STONEYRIDGE_
PICASSO
File src/soc/amd/picasso/chip.h:
Patch Set #2, Line 16: STONEYRIDGE
PICASSO
Patch Set #2, Line 17: STONEYRIDG
PICASSO
Patch Set #2, Line 30: STONEY
PICASSO
Patch Set #2, Line 77: stoneyridge
picasso
Patch Set #2, Line 81: STONEYRIDG
PICASSO
File src/soc/amd/picasso/chip.c:
Patch Set #2, Line 35: stoneyridge
picasso
Patch Set #2, Line 150: stoneyridg
picasso
Patch Set #2, Line 151: StoneyRidge
Picasso
File src/soc/amd/picasso/include/soc/acpi.h:
Patch Set #2, Line 18: STONEYRIDGE
PICASSO
Patch Set #2, Line 19: STONEYRIDGE
PICASSO
Patch Set #2, Line 23: STONEYRIDGE
PICASSO
Patch Set #2, Line 40: STONEYRIDGE
PICASSO
File src/soc/amd/picasso/include/soc/cpu.h:
Patch Set #2, Line 16: STONEYRIDGE
PICASSO
Patch Set #2, Line 17: STONEYRIDGE
PICASSO
Patch Set #2, Line 35: STONEYRIDGE
PICASSO
File src/soc/amd/picasso/include/soc/gpio.h:
Patch Set #2, Line 16: STONEYRIDGE
PICASSO
Patch Set #2, Line 17: STONEYRIDGE
PICASSO
Patch Set #2, Line 308: STONEYRIDGE
PICASSO
File src/soc/amd/picasso/include/soc/i2c.h:
Patch Set #2, Line 16: STONEYRIDGE
PICASSO
Patch Set #2, Line 17: STONEYRIDGE
PICASSO
Patch Set #2, Line 49: STONEYRIDGE
PICASSO
File src/soc/amd/picasso/include/soc/iomap.h:
Patch Set #2, Line 17: STONEYRIDGE
PICASSO
Patch Set #2, Line 18: TONEYRIDGE
PICASSO
Patch Set #2, Line 88: STONEYRIDGE
PICASSO
File src/soc/amd/picasso/include/soc/northbridge.h:
Patch Set #2, Line 17: STONEYRIDGE
PICASSO
Patch Set #2, Line 18: STONEYRIDGE
PICASSO
Patch Set #2, Line 133: STONEYRID
PICASSO
File src/soc/amd/picasso/include/soc/nvs.h:
Patch Set #2, Line 20: stoneyridge
picasso
Patch Set #2, Line 24: STONEYRIDGE
PICASSO
Patch Set #2, Line 25: STONEYRIDGE
PICASSO
Patch Set #2, Line 67: STONEYRIDGE
PICASSO
File src/soc/amd/picasso/include/soc/pci_devs.h:
Patch Set #2, Line 16: STONEYRIDGE
PICASSO
Patch Set #2, Line 17: STONEYRIDGE
PICASSO
Patch Set #2, Line 198: STONEYRIDGE
PICASSO
File src/soc/amd/picasso/include/soc/romstage.h:
Patch Set #2, Line 16: #ifndef __STONEYRIDGE_ROMSTAGE_H__
PICASSO all over
File src/soc/amd/picasso/include/soc/smbus.h:
Patch Set #2, Line 16: __STONEYRIDGE_SMBUS_H__
PICASSO, 3 places
File src/soc/amd/picasso/include/soc/smi.h:
ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
PICASSO
Patch Set #2, Line 242: __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
PICASSO
File src/soc/amd/picasso/include/soc/southbridge.h:
Patch Set #2, Line 17: TONEYRIDGE
PICASSO
Patch Set #2, Line 18: STONEYRIDG
PICASSO
Patch Set #2, Line 319: stoneyridge
picasso
Patch Set #2, Line 415: __STONEYRIDGE_H__
PICASSO
File src/soc/amd/picasso/makefile.inc:
Patch Set #2, Line 30: ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
PICASSO, what socket type?
Patch Set #2, Line 40: STONEYRIDGE
PICASSO
Patch Set #2, Line 66: STONEYRIDGE
PICASSO
Patch Set #2, Line 78: STONEYRIDGE
PICASSO
Patch Set #2, Line 84: STONEYRIDGE
PICASSO
Patch Set #2, Line 109: STONEYRIDGE
PICASSO
Patch Set #2, Line 125: stoneyridge
picasso
Patch Set #2, Line 126: stoneyridge
picasso
Patch Set #2, Line 127: stoneyridge
picasso
Patch Set #2, Line 138: STONEYRIDGE
PICASSO
Patch Set #2, Line 218: STONEYRIDGE
PICASSO
Patch Set #2, Line 219: STONEYRIDGE
PICASSO
Patch Set #2, Line 238: STONEYRIDG
PICASSO
Patch Set #2, Line 239: STONEYRIDGE
PICASSO
Patch Set #2, Line 268: STONEYRIDGE
PICASSO
Patch Set #2, Line 276: STONEYRIDGE
PICASSO
Patch Set #2, Line 283: STONEYRIDGE
PICASSO
Patch Set #2, Line 286: STONEYRIDGE
PICASSO
Patch Set #2, Line 292: STONEYRIDGE
PICASSO
Patch Set #2, Line 316: endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y)
PICASSO, what socket type?
File src/soc/amd/picasso/northbridge.c:
Patch Set #2, Line 280: AGESA
Will it be AGESA or FSP at the end? same in other places bellow.
Patch Set #2, Line 350: family15
family17
family17
File src/soc/amd/picasso/romstage.c:
* TODO: This is a hack to work around current AGESA behavior.
* AGESA needs to change to reflect that coreboot owns
* the MTRRs.
*
* After setting up DRAM, AGESA also completes the configuration
* of the MTRRs, setting regions to WB. Anything written to
* memory between now and and when CAR is dismantled will be
* in cache and lost. For now, set the regions UC to ensure
* the writes get to DRAM.
*/
Really? Say it's a copy from stoney, and that needs to be reviewed in the near future, once AGESA/FSP is solved.
File src/soc/amd/picasso/southbridge.c:
Patch Set #2, Line 59: STONEYRIDGE
PICASSO
Patch Set #2, Line 60: STONEYRIDGE
same
Patch Set #2, Line 66: STONEYRIDGE
same
Patch Set #2, Line 67: STONEYRIDG
same
Patch Set #2, Line 73: STONEYRIDGE
same
Patch Set #2, Line 74: STONEYRIDGE
same
Patch Set #2, Line 80: STONEYRIDGE
same
Patch Set #2, Line 94: STONEYRIDGE
same
File src/soc/amd/picasso/tsc_freq.c:
Patch Set #2, Line 33: amily 15h Models 70h-7F
Wrong, family 17h models ?
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