Hung-Te Lin submitted this change.

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Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved
soc/intel/cannonlake: Drop unreferenced devicetree settings

No mainboard uses these settings, nor does SoC code. Drop them.

Change-Id: Ia9c8347cad479c6b4e678630921f768e0fdee6d9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
---
M src/soc/intel/cannonlake/chip.h
1 file changed, 0 insertions(+), 32 deletions(-)

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 70aab92..492ebca 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -78,24 +78,6 @@
/* TCC activation offset */
uint32_t tcc_offset;

- uint64_t PlatformMemorySize;
- uint8_t SmramMask;
- uint8_t MrcFastBoot;
- uint32_t TsegSize;
- uint16_t MmioSize;
-
- /* DDR Frequency Limit. Maximum Memory Frequency Selections in Mhz.
- * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
- uint16_t DdrFreqLimit;
-
- /* SAGV Low Frequency Selections in Mhz.
- * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
- uint16_t FreqSaGvLow;
-
- /* SAGV Mid Frequency Selections in Mhz.
- * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
- uint16_t FreqSaGvMid;
-
/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
* For CNL, options are as following
* When enabled, memory will be training at three different frequencies.
@@ -119,7 +101,6 @@
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];
- uint8_t SsicPortEnable;
/* Wake Enable Bitmap for USB2 ports */
uint16_t usb2_wake_enable_bitmap;
/* Wake Enable Bitmap for USB3 ports */
@@ -222,27 +203,14 @@
/* Enable/disable SD card write protect pin configuration on CML */
uint8_t ScsSdCardWpPinEnabled;

- /* Integrated Sensor */
- uint8_t PchIshEnable;
-
/* Heci related */
uint8_t DisableHeciRetry;

/* Gfx related */
- uint8_t IgdDvmt50PreAlloc;
uint8_t SkipExtGfxScan;

- uint32_t GraphicsConfigPtr;
uint8_t Device4Enable;

- /* GPIO IRQ Select. The valid value is 14 or 15 */
- uint8_t GpioIrqRoute;
- /* SCI IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
- uint8_t SciIrqSelect;
- /* TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
- uint8_t TcoIrqSelect;
- uint8_t TcoIrqEnable;
-
/* CPU PL2/4 Config
* Performance: Maximum PLs for maximum performance.
* Baseline: Baseline PLs for balanced performance at lower power.

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia9c8347cad479c6b4e678630921f768e0fdee6d9
Gerrit-Change-Number: 48567
Gerrit-PatchSet: 2
Gerrit-Owner: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Felix Singer <felixsinger@posteo.net>
Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte@chromium.org>
Gerrit-Reviewer: Michael Niewöhner <foss@mniewoehner.de>
Gerrit-Reviewer: Nico Huber <nico.h@gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: merged