Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nico Huber, Paul Menzel, Raul Rangel, Subrata Banik.
Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77556?usp=email )
Change subject: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs
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Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77556/comment/3796abf0_a8dfe22f :
PS3, Line 43: +--------------------+--------------------------+--------------------------+-------------------------+
Not sure if the long tables are necessary as only a single item changes. […]
Just because it's not an issue in one program's git log function doesn't mean it isn't in others. There are lots of different tools and there's a reason for the rule to wrap at 72/75 characters.
Commit Message:
https://review.coreboot.org/c/coreboot/+/77556/comment/b9770820_0a5865b0 :
PS6, Line 21: cache post in FSP-S (at ramstage). Hence, this patch provides an API to
Nit: this sentence needs to be rephrased.
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