nsekar@codeaurora.org has uploaded this change for review.

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qcs405: Combine BB with QC-Sec for ROM boot

TEST=build & run

Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
---
M src/soc/qualcomm/qcs405/Makefile.inc
1 file changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29958/1

diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc
index f05c987..158ce34 100644
--- a/src/soc/qualcomm/qcs405/Makefile.inc
+++ b/src/soc/qualcomm/qcs405/Makefile.inc
@@ -31,8 +31,34 @@
 
 CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include
 
+QCS405_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/qcs405
+
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	@printf "Generating: $(subst $(obj)/,,$(@))\n"
 	cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin
 
+################################################################################
+QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn
+qc_sec_file := $(shell ls $(QC_SEC_FILE))
+ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file)))
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf
+	@util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \
+		-x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \
+		-a 64 -d 32 -c 32
+ifeq ($(CONFIG_QC_FLASH_SIMULATE_SDCARD),y)
+	@printf "\nqgpt.py 512 sector size\n"
+	@util/qualcomm/qgpt.py -s 512 $(objcbfs)/merged_bb_qcsec.mbn \
+		$(objcbfs)/bootblock.bin
+else
+	@printf "\nqgpt.py 4K sector size\n"
+	@util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \
+		$(objcbfs)/bootblock.bin
+endif
+
+else
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	@printf "Generating: $(subst $(obj)/,,$(@))\n"
+	cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin
+endif
+
 endif

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