Matt DeVillier has uploaded this change for review.
soc/amd/common/blk/pcie: Program LTR max latencies
PCIe bridges need to provide the LTR (latency tolernace reporting)
maximum snoop/non-snoop values so that they are inherited by downstream
PCIe devices which support and enable LTR. Without this, downstream
devices cannot have LTR enabled, which is a requirement for supporting
PCIe L1 substates. Enabling L1ss without LTR has unpredictable behavior,
including some devices refusing to enter L1 low power modes at all.
BUG=b:265890321
TEST=build/boot google/skyrim (multiple variants, NVMe drives), ensure
LTR is enabled, latency values are correctly set, and that device
power draw at idle is in the expected range (<25 mW).
Change-Id: Icf188e69cf5676be870873c56d175423d16704b4
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
---
M src/soc/amd/common/block/pci/pcie_gpp.c
1 file changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/74288/1
diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c
index 0ce3268..5df1cb1 100644
--- a/src/soc/amd/common/block/pci/pcie_gpp.c
+++ b/src/soc/amd/common/block/pci/pcie_gpp.c
@@ -47,6 +47,20 @@
acpigen_pop_len(); /* Scope */
}
+/* Latency tolerance reporting, max snoop/non-snoop latency value 1.047ms */
+#define PCIE_LTR_MAX_LATENCY_1047US 0x1001
+
+static void pcie_get_ltr_max_latencies(u16 *max_snoop, u16 *max_nosnoop)
+{
+ *max_snoop = PCIE_LTR_MAX_LATENCY_1047US;
+ *max_nosnoop = PCIE_LTR_MAX_LATENCY_1047US;
+}
+
+static struct pci_operations pcie_ops = {
+ .get_ltr_max_latencies = pcie_get_ltr_max_latencies,
+ .set_subsystem = pci_dev_set_subsystem,
+};
+
struct device_operations amd_internal_pcie_gpp_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
@@ -65,4 +79,5 @@
.reset_bus = pci_bus_reset,
.acpi_name = pcie_gpp_acpi_name,
.acpi_fill_ssdt = acpi_device_write_gpp_pci_dev,
+ .ops_pci = &pcie_ops,
};
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