Arthur Heymans has uploaded this change for review.
[TOTEST]soc/intel/baytrail: Implement C_ENVIRONMENT_BOOTBLOCK
untested.
Change-Id: I81cc5904d88d8aea523163d16644b228f53575d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/baytrail/Makefile.inc
A src/soc/intel/baytrail/bootblock/Makefile.inc
M src/soc/intel/baytrail/bootblock/bootblock.c
R src/soc/intel/baytrail/bootblock/uart.c
A src/soc/intel/baytrail/include/soc/bootblock.h
M src/soc/intel/baytrail/include/soc/romstage.h
M src/soc/intel/baytrail/pmutil.c
M src/soc/intel/baytrail/romstage/Makefile.inc
M src/soc/intel/baytrail/romstage/pmc.c
M src/soc/intel/baytrail/romstage/romstage.c
11 files changed, 118 insertions(+), 101 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32970/1
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 03ad31d..f71fc02 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -41,14 +41,12 @@
select POSTCAR_CONSOLE
select CPU_INTEL_COMMON
select CPU_HAS_L2_ENABLE_MSR
+ select C_ENVIRONMENT_BOOTBLOCK
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
- select VBOOT_STARTS_IN_ROMSTAGE
-
-config BOOTBLOCK_CPU_INIT
- string
- default "soc/intel/baytrail/bootblock/bootblock.c"
+ select VBOOT_STARTS_IN_BOOTBLOCK
+ select VBOOT_SEPARATE_VERSTAGE
config MMCONF_BASE_ADDRESS
hex
@@ -94,6 +92,13 @@
bool "Enable MRC RMT training + debug prints"
default n
+# The UEFI System Agent binary needs to be at a fixed offset in the flash
+# and can therefore only reside in the COREBOOT fmap region
+config RO_REGION_ONLY
+ string
+ depends on VBOOT
+ default "mrc.bin"
+
# Cache As RAM region layout:
#
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE
@@ -132,6 +137,13 @@
help
The amount of cache-as-ram region required by the reference code.
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
+
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."
default n
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 6e6eb9c..e6a5704 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -1,6 +1,7 @@
ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y)
subdirs-y += romstage
+subdirs-y += bootblock
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/smm
@@ -12,13 +13,16 @@
ramstage-y += memmap.c
romstage-y += memmap.c
postcar-y += memmap.c
+bootblock-y += tsc_freq.c
ramstage-y += tsc_freq.c
romstage-y += tsc_freq.c
postcar-y += tsc_freq.c
smm-y += tsc_freq.c
+verstage-y += tsc_freq.c
romstage-y += spi.c
postcar-y += spi.c
ramstage-y += spi.c
+verstage-y += spi.c
smm-y += spi.c
ramstage-y += chip.c
ramstage-y += gfx.c
@@ -30,6 +34,8 @@
ramstage-y += ramstage.c
ramstage-y += gpio.c
ramstage-y += cpu.c
+bootblock-y += pmutil.c
+verstage-y += pmutil.c
romstage-y += pmutil.c
ramstage-y += pmutil.c
smm-y += pmutil.c
diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc
new file mode 100644
index 0000000..d093550
--- /dev/null
+++ b/src/soc/intel/baytrail/bootblock/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += ../../../../cpu/intel/car/bootblock.c
+bootblock-y += ../../../../cpu/intel/car/non-evict/cache_as_ram.S
+bootblock-y += ../../../../cpu/x86/early_reset.S
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c
index b2cdf9d..d371a98 100644
--- a/src/soc/intel/baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/baytrail/bootblock/bootblock.c
@@ -18,32 +18,56 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <soc/iosf.h>
-#include <cpu/intel/microcode/microcode.c>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/spi.h>
+#include <soc/pmc.h>
+#include <soc/bootblock.h>
+#include <cpu/intel/car/bootblock.h>
-static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
+static void program_base_addresses(void)
{
- msr_t basem, maskm;
- basem.lo = base | type;
- basem.hi = 0;
- wrmsr(MTRR_PHYS_BASE(reg), basem);
- maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
- maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRR_PHYS_MASK(reg), maskm);
+ uint32_t reg;
+ const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
+
+ /* Memory Mapped IO registers. */
+ reg = PMC_BASE_ADDRESS | 2;
+ pci_write_config32(lpc_dev, PBASE, reg);
+ reg = IO_BASE_ADDRESS | 2;
+ pci_write_config32(lpc_dev, IOBASE, reg);
+ reg = ILB_BASE_ADDRESS | 2;
+ pci_write_config32(lpc_dev, IBASE, reg);
+ reg = SPI_BASE_ADDRESS | 2;
+ pci_write_config32(lpc_dev, SBASE, reg);
+ reg = MPHY_BASE_ADDRESS | 2;
+ pci_write_config32(lpc_dev, MPBASE, reg);
+ reg = PUNIT_BASE_ADDRESS | 2;
+ pci_write_config32(lpc_dev, PUBASE, reg);
+ reg = RCBA_BASE_ADDRESS | 1;
+ pci_write_config32(lpc_dev, RCBA, reg);
+
+ /* IO Port Registers. */
+ reg = ACPI_BASE_ADDRESS | 2;
+ pci_write_config32(lpc_dev, ABASE, reg);
+ reg = GPIO_BASE_ADDRESS | 2;
+ pci_write_config32(lpc_dev, GBASE, reg);
}
-static void enable_rom_caching(void)
+static void spi_init(void)
{
- msr_t msr;
+ u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS);
+ u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
+ uint32_t reg;
- disable_cache();
- /* Why only top 4MiB ? */
- set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
- enable_cache();
-
- /* Enable Variable MTRRs */
- msr.hi = 0x00000000;
- msr.lo = 0x00000800;
- wrmsr(MTRR_DEF_TYPE_MSR, msr);
+ /* Disable generating SMI when setting WPD bit. */
+ write32(scs, read32(scs) & ~SMIWPEN);
+ /*
+ * Enable caching and prefetching in the SPI controller. Disable
+ * the SMM-only BIOS write and set WPD bit.
+ */
+ reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
+ reg &= ~EISS;
+ write32(bcr, reg);
}
static void setup_mmconfig(void)
@@ -64,12 +88,22 @@
pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
}
-static void bootblock_cpu_init(void)
+static void tco_disable(void)
+{
+ uint32_t reg;
+
+ reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
+ reg |= TCO_TMR_HALT;
+ outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
+}
+
+void bootblock_early_cpu_init(void)
{
/* Allow memory-mapped PCI config access. */
setup_mmconfig();
- /* Load microcode before any caching. */
- intel_update_microcode_from_cbfs();
- enable_rom_caching();
+ program_base_addresses();
+ tco_disable();
+ byt_config_com1_and_enable();
+ spi_init();
}
diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/bootblock/uart.c
similarity index 96%
rename from src/soc/intel/baytrail/romstage/uart.c
rename to src/soc/intel/baytrail/bootblock/uart.c
index f9f2fe4..e5788cb 100644
--- a/src/soc/intel/baytrail/romstage/uart.c
+++ b/src/soc/intel/baytrail/bootblock/uart.c
@@ -18,7 +18,7 @@
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
-#include <soc/romstage.h>
+#include <soc/bootblock.h>
void byt_config_com1_and_enable(void)
{
diff --git a/src/soc/intel/baytrail/include/soc/bootblock.h b/src/soc/intel/baytrail/include/soc/bootblock.h
new file mode 100644
index 0000000..65ba6bb
--- /dev/null
+++ b/src/soc/intel/baytrail/include/soc/bootblock.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BAYTRAIL_BOOTBLOCK_H_
+#define _BAYTRAIL_BOOTBLOCK_H_
+
+#if CONFIG(ENABLE_BUILTIN_COM1)
+void byt_config_com1_and_enable(void);
+#else
+static inline void byt_config_com1_and_enable(void) { }
+#endif
+
+
+#endif /* _BAYTRAIL_BOOTBLOCK_H_ */
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h
index 7730893..248112f 100644
--- a/src/soc/intel/baytrail/include/soc/romstage.h
+++ b/src/soc/intel/baytrail/include/soc/romstage.h
@@ -27,15 +27,8 @@
void mainboard_pre_raminit(struct mrc_params *mrc_params);
void raminit(struct mrc_params *mp, int prev_sleep_state);
void gfx_init(void);
-void tco_disable(void);
void punit_init(void);
void set_max_freq(void);
int early_spi_read_wpsr(u8 *sr);
-#if CONFIG(ENABLE_BUILTIN_COM1)
-void byt_config_com1_and_enable(void);
-#else
-static inline void byt_config_com1_and_enable(void) { }
-#endif
-
#endif /* _BAYTRAIL_ROMSTAGE_H_ */
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index b740a03..1fa22f6 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -369,7 +369,12 @@
{
uint32_t gen_pmcon1;
int rtc_fail;
+
+#if !(ENV_BOOTBLOCK || ENV_VERSTAGE)
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+#else
+ struct chipset_power_state *ps = NULL;
+#endif
if (ps != NULL)
gen_pmcon1 = ps->gen_pmcon1;
diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc
index 8f009bd..afab9c0 100644
--- a/src/soc/intel/baytrail/romstage/Makefile.inc
+++ b/src/soc/intel/baytrail/romstage/Makefile.inc
@@ -1,9 +1,7 @@
-cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
cpu_incs-y += $(obj)/fmap_config.h
romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += raminit.c
-romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
romstage-y += gfx.c
romstage-y += pmc.c
romstage-y += early_spi.c
diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c
index 596ed11..9fc3538 100644
--- a/src/soc/intel/baytrail/romstage/pmc.c
+++ b/src/soc/intel/baytrail/romstage/pmc.c
@@ -27,15 +27,6 @@
#include <soc/romstage.h>
#include "../chip.h"
-void tco_disable(void)
-{
- uint32_t reg;
-
- reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
- reg |= TCO_TMR_HALT;
- outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
-}
-
/* This sequence signals the PUNIT to start running. */
void punit_init(void)
{
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 2a530b4..a9b6566 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -50,51 +50,6 @@
* Because we can't use global variables the stack is used for allocations --
* thus the need to call back and forth. */
-static void program_base_addresses(void)
-{
- uint32_t reg;
- const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
-
- /* Memory Mapped IO registers. */
- reg = PMC_BASE_ADDRESS | 2;
- pci_write_config32(lpc_dev, PBASE, reg);
- reg = IO_BASE_ADDRESS | 2;
- pci_write_config32(lpc_dev, IOBASE, reg);
- reg = ILB_BASE_ADDRESS | 2;
- pci_write_config32(lpc_dev, IBASE, reg);
- reg = SPI_BASE_ADDRESS | 2;
- pci_write_config32(lpc_dev, SBASE, reg);
- reg = MPHY_BASE_ADDRESS | 2;
- pci_write_config32(lpc_dev, MPBASE, reg);
- reg = PUNIT_BASE_ADDRESS | 2;
- pci_write_config32(lpc_dev, PUBASE, reg);
- reg = RCBA_BASE_ADDRESS | 1;
- pci_write_config32(lpc_dev, RCBA, reg);
-
- /* IO Port Registers. */
- reg = ACPI_BASE_ADDRESS | 2;
- pci_write_config32(lpc_dev, ABASE, reg);
- reg = GPIO_BASE_ADDRESS | 2;
- pci_write_config32(lpc_dev, GBASE, reg);
-}
-
-static void spi_init(void)
-{
- u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS);
- u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
- uint32_t reg;
-
- /* Disable generating SMI when setting WPD bit. */
- write32(scs, read32(scs) & ~SMIWPEN);
- /*
- * Enable caching and prefetching in the SPI controller. Disable
- * the SMM-only BIOS write and set WPD bit.
- */
- reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
- reg &= ~EISS;
- write32(bcr, reg);
-}
-
static struct chipset_power_state power_state;
static void migrate_power_state(int is_recovery)
@@ -171,16 +126,8 @@
struct chipset_power_state *ps;
int prev_sleep_state;
- program_base_addresses();
-
- tco_disable();
-
- byt_config_com1_and_enable();
-
console_init();
- spi_init();
-
set_max_freq();
punit_init();
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