3 comments:
File src/soc/intel/braswell/Makefile.inc:
Patch Set #3, Line 42: ramstage-y += smbus.c
I don't see how this could work in ramstage. The PCI device is […]
Since I will use it for SPD retrieval only, I may remove it from ramstage
File src/soc/intel/braswell/smbus.c:
Patch Set #3, Line 18: #include <device/pci_def.h>
is this needed?
Yes, for the PCI_BASE_ADDRESS_4, PCI_COMMAND and PCI_COMMAND_IO values
/* Disable interrupts */
REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
/* Clear errors */
REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
The sb/common driver should handle these.
Yes, it clears the errors and interrupts on command setup. I will test without these.
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