Angel Pons has uploaded this change for review.

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soc/intel/broadwell/northbridge.c: Use TXT DPR definition

Taken directly from Haswell.

Change-Id: I06b2348e379b61af60336ea1c4722bcddd953ebc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/soc/intel/broadwell/northbridge.c
1 file changed, 11 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46988/1

diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c
index eb8b5f0..4e75721 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/soc/intel/broadwell/northbridge.c
@@ -8,6 +8,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <security/intel/txt/txt_register.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/intel/broadwell/memmap.h>
 #include <cpu/intel/haswell/haswell.h>
@@ -266,8 +267,6 @@
 	unsigned long base_k, size_k, touud_k, index;
 	struct resource *resource;
 	uint64_t mc_values[NUM_MAP_ENTRIES];
-	unsigned long dpr_size = 0;
-	u32 dpr_reg;
 
 	/* Read in the MAP registers and report their values */
 	mc_read_map_entries(dev, &mc_values[0]);
@@ -275,15 +274,14 @@
 
 	/*
 	 * DMA Protected Range can be reserved below TSEG for PCODE patch
-	 * or TXT/BootGuard related data.  Rather than report a base address
+	 * or TXT/BootGuard related data.  Rather than report a base address,
 	 * the DPR register reports the TOP of the region, which is the same
-	 * as TSEG base.  The region size is reported in MiB in bits 11:4.
+	 * as TSEG base. The region size is reported in MiB in bits 11:4.
 	 */
-	dpr_reg = pci_read_config32(dev, DPR);
-	if (dpr_reg & DPR_EPM) {
-		dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16;
-		printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);
-	}
+	const union dpr_register dpr = {
+		.raw = pci_read_config32(dev, DPR),
+	};
+	printk(BIOS_DEBUG, "MC MAP: DPR: 0x%x\n", dpr.raw);
 
 	/*
 	 * These are the host memory ranges that should be added:
@@ -321,16 +319,15 @@
 	/* 0xc0000 -> TSEG - DPR */
 	base_k = 0xc0000 >> 10;
 	size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
-	size_k -= dpr_size >> 10;
+	size_k -= dpr.size >> 10;
 	ram_resource(dev, index++, base_k, size_k);
 
 	/* TSEG - DPR -> BGSM */
 	resource = new_resource(dev, index++);
-	resource->base = mc_values[TSEG_REG] - dpr_size;
+	resource->base = mc_values[TSEG_REG] - dpr.size;
 	resource->size = mc_values[BGSM_REG] - resource->base;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
-			  IORESOURCE_STORED | IORESOURCE_RESERVE |
-			  IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+			  IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
 
 	/* BGSM -> TOLUD */
 	resource = new_resource(dev, index++);

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