Martin Roth has uploaded this change for review.

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soc/amd/picasso: Change header guards from stoney to picasso

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356
---
M src/soc/amd/picasso/include/soc/acpi.h
M src/soc/amd/picasso/include/soc/cpu.h
M src/soc/amd/picasso/include/soc/gpio.h
M src/soc/amd/picasso/include/soc/iomap.h
M src/soc/amd/picasso/include/soc/northbridge.h
M src/soc/amd/picasso/include/soc/nvs.h
M src/soc/amd/picasso/include/soc/pci_devs.h
M src/soc/amd/picasso/include/soc/romstage.h
M src/soc/amd/picasso/include/soc/smbus.h
M src/soc/amd/picasso/include/soc/smi.h
M src/soc/amd/picasso/include/soc/southbridge.h
11 files changed, 33 insertions(+), 33 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32409/1

diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h
index 15a41ed..71fe10e 100644
--- a/src/soc/amd/picasso/include/soc/acpi.h
+++ b/src/soc/amd/picasso/include/soc/acpi.h
@@ -15,8 +15,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __SOC_STONEYRIDGE_ACPI_H__
-#define __SOC_STONEYRIDGE_ACPI_H__
+#ifndef __SOC_PICASSO_ACPI_H__
+#define __SOC_PICASSO_ACPI_H__
 
 #include <arch/acpi.h>
 
@@ -37,4 +37,4 @@
 
 const char *soc_acpi_name(const struct device *dev);
 
-#endif /* __SOC_STONEYRIDGE_ACPI_H__ */
+#endif /* __SOC_PICASSO_ACPI_H__ */
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index 934a9f2..d9d48ad 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_CPU_H__
-#define __STONEYRIDGE_CPU_H__
+#ifndef __PICASSO_CPU_H__
+#define __PICASSO_CPU_H__
 
 #include <device/device.h>
 
@@ -32,4 +32,4 @@
 void stoney_init_cpus(struct device *dev);
 void check_mca(void);
 
-#endif /* __STONEYRIDGE_CPU_H__ */
+#endif /* __PICASSO_CPU_H__ */
diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h
index fe8240f..94d3eef 100644
--- a/src/soc/amd/picasso/include/soc/gpio.h
+++ b/src/soc/amd/picasso/include/soc/gpio.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_GPIO_H__
-#define __STONEYRIDGE_GPIO_H__
+#ifndef __PICASSO_GPIO_H__
+#define __PICASSO_GPIO_H__
 
 #define GPIO_DEVICE_NAME	"AMD0030"
 #define GPIO_DEVICE_DESC	"GPIO Controller"
@@ -605,4 +605,4 @@
 int gpio_interrupt_status(gpio_t gpio);
 
 #endif /* __ACPI__ */
-#endif /* __STONEYRIDGE_GPIO_H__ */
+#endif /* __PICASSO_GPIO_H__ */
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 613dd04..277a8fb 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -14,8 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __SOC_STONEYRIDGE_IOMAP_H__
-#define __SOC_STONEYRIDGE_IOMAP_H__
+#ifndef __SOC_PICASSO_IOMAP_H__
+#define __SOC_PICASSO_IOMAP_H__
 
 /* MMIO Ranges */
 #define PSP_MAILBOX_BAR3_BASE		0xf0a00000
@@ -79,4 +79,4 @@
 #define BIOSRAM_UMA_SIZE		0xf4 /* 4 bytes */
 #define BIOSRAM_UMA_BASE		0xf8 /* 8 bytes */
 
-#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */
+#endif /* __SOC_PICASSO_IOMAP_H__ */
diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h
index 563dae0..8405e9c 100644
--- a/src/soc/amd/picasso/include/soc/northbridge.h
+++ b/src/soc/amd/picasso/include/soc/northbridge.h
@@ -14,8 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__
-#define __PI_STONEYRIDGE_NORTHBRIDGE_H__
+#ifndef __PI_PICASSO_NORTHBRIDGE_H__
+#define __PI_PICASSO_NORTHBRIDGE_H__
 
 #include <device/device.h>
 
@@ -129,4 +129,4 @@
 void set_warm_reset_flag(void);
 int is_warm_reset(void);
 
-#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */
+#endif /* __PI_PICASSO_NORTHBRIDGE_H__ */
diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h
index 08d4697..8ce5da6 100644
--- a/src/soc/amd/picasso/include/soc/nvs.h
+++ b/src/soc/amd/picasso/include/soc/nvs.h
@@ -21,8 +21,8 @@
  *
  */
 
-#ifndef __SOC_STONEYRIDGE_NVS_H__
-#define __SOC_STONEYRIDGE_NVS_H__
+#ifndef __SOC_PICASSO_NVS_H__
+#define __SOC_PICASSO_NVS_H__
 
 #include <commonlib/helpers.h>
 #include <stdint.h>
@@ -64,4 +64,4 @@
 } __packed global_nvs_t;
 check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
 
-#endif /* __SOC_STONEYRIDGE_NVS_H__ */
+#endif /* __SOC_PICASSO_NVS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h
index 02fed7a..478a2cb 100644
--- a/src/soc/amd/picasso/include/soc/pci_devs.h
+++ b/src/soc/amd/picasso/include/soc/pci_devs.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__
-#define __PI_STONEYRIDGE_PCI_DEVS_H__
+#ifndef __PI_PICASSO_PCI_DEVS_H__
+#define __PI_PICASSO_PCI_DEVS_H__
 
 #include <device/pci_def.h>
 
@@ -195,4 +195,4 @@
 #define SD_DEVFN		PCI_DEVFN(SD_DEV, SD_FUNC)
 #define SOC_SD_DEV		_SOC_DEV(SD_DEV, SD_FUNC)
 
-#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */
+#endif /* __PI_PICASSO_PCI_DEVS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h
index 6ce79b4..d8b2900 100644
--- a/src/soc/amd/picasso/include/soc/romstage.h
+++ b/src/soc/amd/picasso/include/soc/romstage.h
@@ -13,9 +13,9 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_ROMSTAGE_H__
-#define __STONEYRIDGE_ROMSTAGE_H__
+#ifndef __PICASSO_ROMSTAGE_H__
+#define __PICASSO_ROMSTAGE_H__
 
 void mainboard_romstage_entry(int s3_resume);
 
-#endif /* __STONEYRIDGE_ROMSTAGE_H__ */
+#endif /* __PICASSO_ROMSTAGE_H__ */
diff --git a/src/soc/amd/picasso/include/soc/smbus.h b/src/soc/amd/picasso/include/soc/smbus.h
index 71f7faf..7b05610 100644
--- a/src/soc/amd/picasso/include/soc/smbus.h
+++ b/src/soc/amd/picasso/include/soc/smbus.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_SMBUS_H__
-#define __STONEYRIDGE_SMBUS_H__
+#ifndef __PICASSO_SMBUS_H__
+#define __PICASSO_SMBUS_H__
 
 #include <stdint.h>
 #include <soc/iomap.h>
@@ -55,4 +55,4 @@
 void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
 void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val);
 
-#endif /* __STONEYRIDGE_SMBUS_H__ */
+#endif /* __PICASSO_SMBUS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h
index d22b8db..46c4a8c 100644
--- a/src/soc/amd/picasso/include/soc/smi.h
+++ b/src/soc/amd/picasso/include/soc/smi.h
@@ -15,8 +15,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
-#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
+#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__
+#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__
 
 
 #define SMI_GEVENTS			24
@@ -238,4 +238,4 @@
 void enable_smi_generation(void);
 #endif
 
-#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */
+#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 9fa93c8..a6d144a 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -14,8 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __STONEYRIDGE_H__
-#define __STONEYRIDGE_H__
+#ifndef __PICASSO_SB_H__
+#define __PICASSO_SB_H__
 
 #include <types.h>
 #include <device/device.h>
@@ -609,4 +609,4 @@
  */
 void set_pm1cnt_s5(void);
 
-#endif /* __STONEYRIDGE_H__ */
+#endif /* __PICASSO_SB_H__ */

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