Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Sugnan Prabhu S, Subrata Banik, Kane Chen, Patrick Rudolph.
Sridhar Siricilla uploaded patch set #3 to this change.
View Change
soc/inte/alderlake: [TEST][PATCH 1/2] Enable hotplug and configure free clock for PCIe RPs
The patch enables hotplug, places PCIe in compliance test mode and
Configures Clock sources to run free for EV test.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib5752bd1586e6062f740ca7a32df2135e26257b9
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/52244/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib5752bd1586e6062f740ca7a32df2135e26257b9
Gerrit-Change-Number: 52244
Gerrit-PatchSet: 3
Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla@intel.com>
Gerrit-Reviewer: Kane Chen <kane.chen@intel.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
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