Shelley Chen submitted this change.

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Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Frans Hendriks: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
mb/google/hatch: Add noise mitigation setting for dratini/jinlon

Enable acoustic noise mitigation, the slow slew rates are fast time divided by 8
and disable Fast PKG C State Ramp (IA, GT, SA).

BRANCH=hatch
BUG=b:143501884
TEST=build and verify that noise reduce.

Change-Id: I65f47288a7b1da98296fdba87ab5ca0c3a567aaf
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38212
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/google/hatch/variants/dratini/overridetree.cb
M src/mainboard/google/hatch/variants/jinlon/overridetree.cb
2 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb
index f820629..5c30a5a 100644
--- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb
@@ -17,6 +17,15 @@
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"

+ # VR Slew rate setting
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
+ register "SlowSlewRateForSa" = "2"
+ register "FastPkgCRampDisableIa" = "1"
+ register "FastPkgCRampDisableGt" = "1"
+ register "FastPkgCRampDisableSa" = "1"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
index c9613d2..f3f6c3b 100644
--- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -17,6 +17,15 @@
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"

+ # VR Slew rate setting
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
+ register "SlowSlewRateForSa" = "2"
+ register "FastPkgCRampDisableIa" = "1"
+ register "FastPkgCRampDisableGt" = "1"
+ register "FastPkgCRampDisableSa" = "1"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I65f47288a7b1da98296fdba87ab5ca0c3a567aaf
Gerrit-Change-Number: 38212
Gerrit-PatchSet: 6
Gerrit-Owner: Chen Wisley <wisley.chen@quantatw.com>
Gerrit-Reviewer: Chen Wisley <wisley.chen@quantatw.com>
Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com>
Gerrit-Reviewer: Paul Fagerburg <pfagerburg@chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-Reviewer: Philip Chen <philipchen@google.com>
Gerrit-Reviewer: Shelley Chen <shchen@google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: merged