Kyösti Mälkki submitted this change.

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Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Michał Żygowski: Looks good to me, approved
AGESA,binaryPI: Remove early_all_cores()

This was implemented to make sure it gets called before
attempting any PCI MMIO access. Now that we have one
central romstage_main() implementation this extra precaution
is no longer useful.

Change-Id: I09b24da827e00d7a9ba0a51d5eef36f174b893a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
M src/drivers/amd/agesa/cache_as_ram.S
M src/drivers/amd/agesa/romstage.c
M src/include/cpu/amd/car.h
3 files changed, 3 insertions(+), 13 deletions(-)

diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index 3f1358a..e3e5735 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -94,8 +94,6 @@

#endif

- call early_all_cores
-
/* Must maintain 16-byte stack alignment here. */
pushl $0x0
pushl $0x0
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 72aac3e..0ecfeb2 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -27,15 +27,6 @@
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>

-#if !CONFIG(POSTCAR_STAGE)
-#error "Only POSTCAR_STAGE is supported."
-#endif
-
-void asmlinkage early_all_cores(void)
-{
- amd_initmmio();
-}
-
void __weak platform_once(struct sysinfo *cb)
{
board_BeforeAgesa(cb);
@@ -57,6 +48,9 @@
u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24);
int cbmem_initted = 0;

+ /* Enable PCI MMIO configuration. */
+ amd_initmmio();
+
fill_sysinfo(cb);

if ((initial_apic_id == 0) && boot_cpu()) {
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index 59f5bb9..46f7e1d 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -5,8 +5,6 @@

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);

-void asmlinkage early_all_cores(void);
-
void *asmlinkage romstage_main(unsigned long bist);

#endif

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I09b24da827e00d7a9ba0a51d5eef36f174b893a6
Gerrit-Change-Number: 37203
Gerrit-PatchSet: 3
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki@gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki@gmail.com>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski@3mdeb.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: merged