Patrick Georgi merged this change.
superio/ite: Add IT8786E-I
Based on IT8786E-I V0.4.1 datasheet with following remark:
"Please note that the IT8786E-I V0.4.1 is
applicable only to the D version."
Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
M src/superio/ite/Makefile.inc
A src/superio/ite/it8786e/Kconfig
A src/superio/ite/it8786e/Makefile.inc
A src/superio/ite/it8786e/acpi/superio.asl
A src/superio/ite/it8786e/chip.h
A src/superio/ite/it8786e/it8786e.h
A src/superio/ite/it8786e/superio.c
7 files changed, 395 insertions(+), 0 deletions(-)
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index 551abe9..8388c7a 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2018 Libretrend LDA
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -31,3 +32,4 @@
subdirs-y += it8728f
subdirs-y += it8772f
subdirs-y += it8783ef
+subdirs-y += it8786e
diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig
new file mode 100644
index 0000000..9d3f258
--- /dev/null
+++ b/src/superio/ite/it8786e/Kconfig
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 secunet Security Networks AG
+## Copyright (C) 2018 Libretrend LDA
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ITE_IT8786E
+ bool
+ select SUPERIO_ITE_COMMON_PRE_RAM
+ select SUPERIO_ITE_ENV_CTRL
+ select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2
+ select SUPERIO_ITE_ENV_CTRL_8BIT_PWM
+ select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG
diff --git a/src/superio/ite/it8786e/Makefile.inc b/src/superio/ite/it8786e/Makefile.inc
new file mode 100644
index 0000000..560957f
--- /dev/null
+++ b/src/superio/ite/it8786e/Makefile.inc
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 secunet Security Networks AG
+## Copyright (C) 2018 Libretrend LDA
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8786E) += superio.c
diff --git a/src/superio/ite/it8786e/acpi/superio.asl b/src/superio/ite/it8786e/acpi/superio.asl
new file mode 100644
index 0000000..f860da6
--- /dev/null
+++ b/src/superio/ite/it8786e/acpi/superio.asl
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
+ * Copyright (C) 2013, 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Include this file into a mainboard's DSDT _SB device tree and it will
+ * expose the IT8786E SuperIO and some of its functionality.
+ *
+ * It allows the change of IO ports, IRQs and DMA settings on logical
+ * devices, disabling and reenabling logical devices.
+ *
+ * LDN State
+ * 0x1 UARTA Implemented, untested
+ * 0x2 UARTB Implemented, untested
+ * 0x3 PP Not implemented
+ * 0x4 EC Not implemented
+ * 0x5 KBC Implemented, untested
+ * 0x6 MOUSE Implemented, untested
+ * 0x7 GPIO Not implemented
+ * 0x8 UARTC Implemented, untested
+ * 0x9 UARTD Implemented, untested
+ * 0xa UARTE Not implemented
+ * 0xb UARTF Not implemented
+ * 0xc CIR Not implemented
+ *
+ * Controllable through preprocessor defines:
+ * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
+ * SUPERIO_PNP_BASE I/O address of the first PnP configuration register
+ * IT8786E_SHOW_UARTA If defined, UARTA will be exposed.
+ * IT8786E_SHOW_UARTB If defined, UARTB will be exposed.
+ * IT8786E_SHOW_UARTC If defined, UARTC will be exposed.
+ * IT8786E_SHOW_UARTD If defined, UARTD will be exposed.
+ * IT8786E_SHOW_KBC If defined, the KBC will be exposed.
+ * IT8786E_SHOW_PS2M If defined, PS/2 mouse support will be exposed.
+ */
+
+#undef SUPERIO_CHIP_NAME
+#define SUPERIO_CHIP_NAME IT8786E
+#include <superio/acpi/pnp.asl>
+
+#undef PNP_DEFAULT_PSC
+#define PNP_DEFAULT_PSC Return (0) /* no power management */
+
+#define CONFIGURE_CONTROL CCTL
+
+Device (SUPERIO_DEV) {
+ Name (_HID, EisaId("PNP0A05"))
+ Name (_STR, Unicode("ITE IT8786E Super I/O"))
+ Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
+
+ /* Mutex for accesses to the configuration ports */
+ Mutex (CRMX, 1)
+
+ /* SuperIO configuration ports */
+ OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
+ Field (CREG, ByteAcc, NoLock, Preserve)
+ {
+ PNP_ADDR_REG, 8,
+ PNP_DATA_REG, 8
+ }
+ IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x02),
+ CONFIGURE_CONTROL, 8, /* Global configure control */
+
+ Offset (0x07),
+ PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
+
+ Offset (0x30),
+ PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
+
+ Offset (0x60),
+ PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
+ PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
+ Offset (0x62),
+ PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
+ PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
+
+ Offset (0x70),
+ PNP_IRQ0, 8, /* First IRQ */
+ }
+
+ Method (_CRS)
+ {
+ /* Announce the used i/o ports to the OS */
+ Return (ResourceTemplate () {
+ IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE,
+ 0x01, 0x02)
+ })
+ }
+
+ #undef PNP_ENTER_MAGIC_1ST
+ #undef PNP_ENTER_MAGIC_2ND
+ #undef PNP_ENTER_MAGIC_3RD
+ #undef PNP_ENTER_MAGIC_4TH
+ #undef PNP_EXIT_MAGIC_1ST
+ #define PNP_ENTER_MAGIC_1ST 0x87
+ #define PNP_ENTER_MAGIC_2ND 0x01
+ #define PNP_ENTER_MAGIC_3RD 0x55
+#if SUPERIO_PNP_BASE == 0x2e
+ #define PNP_ENTER_MAGIC_4TH 0x55
+#else
+ #define PNP_ENTER_MAGIC_4TH 0xaa
+#endif
+ #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL
+ #define PNP_EXIT_SPECIAL_VAL 0x02
+ #include <superio/acpi/pnp_config.asl>
+
+#ifdef IT8786E_SHOW_UARTA
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 1
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef IT8786E_SHOW_UARTB
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 2
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef IT8786E_SHOW_KBC
+ #undef SUPERIO_KBC_LDN
+ #undef SUPERIO_KBC_PS2M
+ #undef SUPERIO_KBC_PS2LDN
+ #define SUPERIO_KBC_LDN 5
+#ifdef IT8786E_SHOW_PS2M
+ #define SUPERIO_KBC_PS2LDN 6
+#endif
+ #include <superio/acpi/pnp_kbc.asl>
+#endif
+
+#ifdef IT8786E_SHOW_UARTC
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 8
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef IT8786E_SHOW_UARTD
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 9
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+}
diff --git a/src/superio/ite/it8786e/chip.h b/src/superio/ite/it8786e/chip.h
new file mode 100644
index 0000000..4b2e811
--- /dev/null
+++ b/src/superio/ite/it8786e/chip.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ * Copyright (C) 2019 Libretrend LDA
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8786E_CHIP_H
+#define SUPERIO_ITE_IT8786E_CHIP_H
+
+#include <superio/ite/common/env_ctrl_chip.h>
+
+struct superio_ite_it8786e_config {
+ struct ite_ec_config ec;
+};
+
+#endif /* SUPERIO_ITE_IT8786E_CHIP_H */
diff --git a/src/superio/ite/it8786e/it8786e.h b/src/superio/ite/it8786e/it8786e.h
new file mode 100644
index 0000000..5f11b63
--- /dev/null
+++ b/src/superio/ite/it8786e/it8786e.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ * Copyright (C) 2019 Libretrend LDA
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8786E_H
+#define SUPERIO_ITE_IT8786E_H
+
+#define IT8786E_SP1 0x01 /* COM1 */
+#define IT8786E_SP2 0x02 /* COM2 */
+#define IT8786E_PP 0x03 /* Printer port */
+#define IT8786E_EC 0x04 /* Environment controller */
+#define IT8786E_KBCK 0x05 /* Keyboard */
+#define IT8786E_KBCM 0x06 /* Mouse */
+#define IT8786E_GPIO 0x07 /* GPIO */
+#define IT8786E_SP3 0x08 /* COM3 */
+#define IT8786E_SP4 0x09 /* COM4 */
+#define IT8786E_CIR 0x0a /* Consumer IR */
+#define IT8786E_SP5 0x0b /* COM5 */
+#define IT8786E_SP6 0x0c /* COM6 */
+
+#include <stdint.h>
+
+#endif /* SUPERIO_ITE_IT8786E_H */
diff --git a/src/superio/ite/it8786e/superio.c b/src/superio/ite/it8786e/superio.c
new file mode 100644
index 0000000..ac9dc4b
--- /dev/null
+++ b/src/superio/ite/it8786e/superio.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ * Copyright (C) 2019 Libretrend LDA
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+#include <superio/conf_mode.h>
+#include <superio/ite/common/env_ctrl.h>
+
+#include "it8786e.h"
+#include "chip.h"
+
+static void it8786e_init(struct device *const dev)
+{
+ const struct superio_ite_it8786e_config *conf;
+ const struct resource *res;
+
+ if (!dev->enabled)
+ return;
+
+ switch (dev->path.pnp.device) {
+ case IT8786E_EC:
+ conf = dev->chip_info;
+ res = find_resource(dev, PNP_IDX_IO0);
+ if (!conf || !res)
+ break;
+ ite_ec_init(res->base, &conf->ec);
+ break;
+ case IT8786E_KBCK:
+ pc_keyboard_init(NO_AUX_DEVICE);
+ break;
+ default:
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = it8786e_init,
+ .ops_pnp_mode = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ /* Serial Port 1 */
+ { NULL, IT8786E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
+ PNP_MSC2,
+ 0x0ff8, },
+ /* Serial Port 2 */
+ { NULL, IT8786E_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
+ PNP_MSC2,
+ 0x0ff8, },
+ /* Printer Port */
+ { NULL, IT8786E_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 |
+ PNP_MSC0,
+ 0x0ff8, 0x0ffc, },
+ /* Environmental Controller */
+ { NULL, IT8786E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 |
+ PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 |
+ PNP_MSC5 | PNP_MSC6 | PNP_MSCA | PNP_MSCB |
+ PNP_MSCC,
+ 0x0ff8, 0x0ffc, },
+ /* KBC Keyboard */
+ { NULL, IT8786E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+ 0x0fff, 0x0fff, },
+ /* KBC Mouse */
+ { NULL, IT8786E_KBCM, PNP_IRQ0 | PNP_MSC0, },
+ /* GPIO */
+ { NULL, IT8786E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0 |
+ PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 |
+ PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 |
+ PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB,
+ 0x0ffc, 0x0fff, },
+ /* Serial Port 3 */
+ { NULL, IT8786E_SP3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
+ PNP_MSC2,
+ 0x0ff8, },
+ /* Serial Port 4 */
+ { NULL, IT8786E_SP4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
+ PNP_MSC2,
+ 0x0ff8, },
+ /* Consumer Infrared */
+ { NULL, IT8786E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
+ /* Serial Port 5 */
+ { NULL, IT8786E_SP5, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
+ PNP_MSC2,
+ 0x0ff8, },
+ /* Serial Port 6 */
+ { NULL, IT8786E_SP6, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 |
+ PNP_MSC2,
+ 0x0ff8, },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8786e_ops = {
+ CHIP_NAME("ITE IT8786E Super I/O")
+ .enable_dev = enable_dev,
+};
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