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3 comments:

• File src/cpu/x86/cache/cache.c:

  • Patch Set #7, Line 27: int clflush_supported(void)

    This is not sufficient. When CAR is active it's microarchitecturally defined how a clflush is handled in CAR mode. You need a way for the chipset to indicate this is valid sequence that can be performed.

  • Patch Set #7, Line 29: 19

    Aren't there defines for these bits instead of open coding them?

  • Patch Set #7, Line 60: if (!cbmem_ready())

    Why is a cbmem check in here? It doesn't immediately make sense why this would be the case. Likewise, this function is also active when not loading postcar, e.g. FSP. What about that? Or are you using cbmem to be an indirect proxy for postcar loading?

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