Attention is currently required from: Subrata Banik, Simon Chou, TimLiu-SMCI, Jonathan Zhang, Johnny Lin, Paul Menzel, David Hendricks, Christian Walter, Angel Pons, Arthur Heymans, Shuming Chu (Shuming), Elyes Haouas.
Jian-Ming Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71945 )
Change subject: soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory ......................................................................
Patch Set 11:
(9 comments)
File src/soc/intel/xeon_sp/ebg/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/71945/comment/0a193515_ab34702b PS8, Line 204: #define GPPC_H8 144 : #define GPPC_H9 145 : #define GPPC_H10 146 : #define GPPC_H11 147 : #define GPPC_H12 148 : #define GPPC_H13 149 : #define GPPC_H14 150
Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept. Please check #606161 page 20, the offset assigned for GPPC_H7 and GPPC_H15.
https://review.coreboot.org/c/coreboot/+/71945/comment/ac335c89_23b8fe67 PS8, Line 227: #define GPP_J9 165 : #define GPP_J10 166 : #define GPP_J11 167
Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept. Please check #606161 page 21, the offset assigned for GPPC_J8 and GPPC_J12.
https://review.coreboot.org/c/coreboot/+/71945/comment/9eb582ba_9a01535f PS8, Line 234: #define GPP_J16 172 : #define GPP_J17 173
Tim, could you check this?
GPP_J15 is the last pad configuration in EDS for GPIO community 4. GPP_J16 and GPP_J17 are defined as unrouted GPIOs in #606161 page 1692.
https://review.coreboot.org/c/coreboot/+/71945/comment/9d8b5432_08dff3a7 PS8, Line 244: define GPP_I3 183 : #define GPP_I4 184 : #define GPP_I5 185 : #define GPP_I6 186 : #define GPP_I7 187 : #define GPP_I8 188 : #define GPP_I9 189 : #define GPP_I10 190 : #define GPP_I11 191
Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept. Please check #606161 page 23, the offset assigned for GPPC_I12.
https://review.coreboot.org/c/coreboot/+/71945/comment/f96f77d7_045cc315 PS8, Line 259: #define GPP_I18 198 : #define GPP_I19 199 : #define GPP_I20 200
Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept. Please check #606161 page 23, the offset assigned for GPPC_I17 and GPPC_I21.
https://review.coreboot.org/c/coreboot/+/71945/comment/cd3eba78_6efeb631 PS8, Line 276: #define GPP_L9 213 : #define GPP_L10 214 : #define GPP_L11 215 : #define GPP_L12 216 : #define GPP_L13 217 : #define GPP_L14 218 : #define GPP_L15 219 : #define GPP_L16 220 : #define GPP_L17 221
Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept. I think the reserved entries are correct based on the calculation of offset of PAD_CFG_DW0_GPP_L_8 and PAD_CFG_DW0_CPP_M_0. Please check #606161 page 24, the offset assigned for GPPC_L8 and GPPC_M0.
https://review.coreboot.org/c/coreboot/+/71945/comment/bff7fea9_b7cecb6d PS8, Line 296: #define GPP_M9 231 : #define GPP_M10 232
Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept. Please check #606161 page 24, the offset assigned for GPPC_M8 and GPPC_M11.
https://review.coreboot.org/c/coreboot/+/71945/comment/f883a01f_ec001f45 PS8, Line 300: #define GPP_M13 235 : #define GPP_M14 236
Tim, could you check this?
They are not declared as unrouted GPIOs in EDS. However the offsets were reserved by Emmitsburg PCH for PAD_CFG_DW* registers for these unused pins. To manage the related offsets, these setting shall be kept. Please check #606161 page 25, the offset assigned for GPPC_M12 and GPPC_M15.
https://review.coreboot.org/c/coreboot/+/71945/comment/3d54e3f4_79f66077 PS8, Line 312: #define GPP_N5 245 : #define GPP_N6 246 : #define GPP_N7 247 : #define GPP_N8 248 : #define GPP_N9 249 : #define GPP_N10 250 : #define GPP_N11 251 : #define GPP_N12 252 : #define GPP_N13 253 : #define GPP_N14 254 : #define GPP_N15 255 : #define GPP_N16 256 : #define GPP_N17 257
Tim, could you check this?
GPP_N4 is the last pad configuration in EDS for GPIO community 5. However, GPP_N5 to GPP_N17 were defined in "Unrouted GPIOs".