[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Implement soc_get_north_xhci_usb_info

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47414 )

Change subject: soc/intel/alderlake: Implement soc_get_north_xhci_usb_info
......................................................................

soc/intel/alderlake: Implement soc_get_north_xhci_usb_info

Alder Lake-P supports 1 USB2 port and 4 USB3 ports on the TCSS XHCI
device.

Change-Id: I57e721dc6fb98aca19fa4c84648c33735aa8f2f0
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/north_xhci.c
2 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/47414/1

diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index f1d7b65..f21ad18 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -37,6 +37,7 @@
 ramstage-y += gpio.c
 ramstage-y += lockdown.c
 ramstage-y += me.c
+ramstage-y += north_xhci.c
 ramstage-y += p2sb.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
diff --git a/src/soc/intel/alderlake/north_xhci.c b/src/soc/intel/alderlake/north_xhci.c
new file mode 100644
index 0000000..5ca6430
--- /dev/null
+++ b/src/soc/intel/alderlake/north_xhci.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/north_xhci.h>
+
+#define USB2_PORT_STATUS_REG	0x480
+#define USB3_PORT_STATUS_REG	0x490
+#define USB2_PORT_NUM		1
+#define USB3_PORT_NUM		4
+
+static const struct north_xhci_usb_info usb_info = {
+	.usb2_port_status_reg = USB2_PORT_STATUS_REG,
+	.num_usb2_ports = USB2_PORT_NUM,
+	.usb3_port_status_reg = USB3_PORT_STATUS_REG,
+	.num_usb3_ports = USB3_PORT_NUM,
+};
+
+const struct north_xhci_usb_info *soc_get_north_xhci_usb_info(void)
+{
+	return &usb_info;
+}