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1 comment:

File src/soc/intel/cannonlake/romstage/romstage.c:
- Patch Set #9, Line 167: /* Cache the ROM as WP just below 4GiB. */
  >> Yes. And cbmem -t with POSTCAR_STAGE=y for comparison.
  localhost ~ # cbmem -t
  58 entries total:
```
   0:1st timestamp                                     12,239
 100:start of postcar                                  307,098 (890)
 101:end of postcar                                    307,099 (0)
  99:selfboot jump                                     647,489 (465)
```
  I am pretty sure this was not with POSTCAR_STAGE=y. Nevertheless, it's now 635ms to enter payload, while it was 650ms before. So I assume this was POSTCAR_STAGE=n with TSEG marked WB cacheable?
  I am still waiting for cbmem -t from POSTCAR_STAGE=y and TSEG marked WB cacheable. That should be your reference point for the commit message.
```
  10:start of ramstage                                 340,347 (351)
  30:device enumeration                                391,132 (50,784)
```
```
  10:start of ramstage                                 333,615 (373)
  30:device enumeration                                379,313 (45,697)
```
  I think none of the changes around POSTCAR MTRRs would have effect after either timestamp 10 or 30 above. So I would use 99:selfboot jmp as the reference.
  1100:finished vboot kernel verification 828,339 (137,616)
  1100:finished vboot kernel verification 831,888 (138,990)
  1100:finished vboot kernel verification 823,294 (147,272)
  Don't stare at the "Total Time" line. Notice how your fastest entry to kernel had the slowest 1100:finished vboot kernel verification.
  IMO this continues be much ado about nothing. You are optimizing at the wrong spot for high price to pay on code complexity (and stability against changes). Until x86 reset is even de-asserted, the hardware probably already has spent over 150ms for the voltage ramp-ups after you toggled the power button.

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