Marshall Dawson submitted this change.
vc/amd/fsp/picasso: Sync FSP-S UPD header file
Sync the UPD definitions with the latest auto-generated files.
Definitions and usage will be updated in a subsequent FSP
Integration Guide.
Cq-Depend: chrome-internal:3247431
BUG=b:167421913, b:166519072, b:159664044
TEST=Boot morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ic85e1f457c8932d933d8645738de68319dbf375a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
M src/vendorcode/amd/fsp/picasso/FspsUpd.h
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h
index 5adbb81..34c672d 100644
--- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h
+++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h
@@ -31,7 +31,11 @@
/** Offset 0x011D**/ uint8_t unused3;
/** Offset 0x011E**/ uint32_t xhci_oc_pin_select;
/** Offset 0x0122**/ uint8_t xhci0_force_gen1;
- /** Offset 0x0123**/ uint8_t UnusedUpdSpace0[45];
+ /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable;
+ /** Offset 0x0124**/ uint32_t gnb_ioapic_base;
+ /** Offset 0x0128**/ uint8_t gnb_ioapic_id;
+ /** Offset 0x0129**/ uint8_t fch_ioapic_id;
+ /** Offset 0x0126**/ uint8_t UnusedUpdSpace0[38];
/** Offset 0x0150**/ uint16_t UpdTerminator;
} FSP_S_CONFIG;
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