Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai.

EricR Lai uploaded patch set #41 to this change.

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soc/intel/alderlake: Refactor PCIE port config

Refactor PCIE port config structure. Make it easier to map from schematic.
We don't have to convert the PCIE ports RP number and CLK source in devicetree.
All the convert will be done by SoC level.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
---
M src/mainboard/intel/adlrvp/devicetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
5 files changed, 128 insertions(+), 88 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/41

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