Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Tim Wawrzynczak, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49130
to look at the new patch set (#3).
Change subject: sb/intel/bd82x6x: Correct xHCI sleep workaround ......................................................................
sb/intel/bd82x6x: Correct xHCI sleep workaround
The S3/S4 workaround is specific to Panther Point stepping A0, and it is wrongly implemented. Rewrite the whole function as per reference code. Since this runs in SMM, be overly cautious and double-check everything.
Do not rely on GNVS to determine if xHCI is enabled. Instead, check whether the corresponding bit in the Function Disable register is set. Only Panther Point has xHCI, so exit early if this is not the case.
Change-Id: Iabce6c52fac781dc694f5b589fab2e9fe438f3f5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/smihandler.c 2 files changed, 77 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/49130/3