Matt DeVillier has uploaded this change for review.

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soc/{baytrail/braswell/broadwell}: fix flashconsole on platform

Enabling flashconsole on these platforms fails to build due to
spi.c not being compiled in prior to ramstage. Include in early stages
(bootblock/romstage/postcar) as needed to enable flashconsole support.

Early inclusion of monotonic_timer.c is needed for Broadwell as well.

Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
---
M src/soc/intel/baytrail/Makefile.inc
M src/soc/intel/braswell/Makefile.inc
M src/soc/intel/broadwell/Makefile.inc
3 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32878/1
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 0d4bac5..6e6eb9c 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -16,6 +16,8 @@
romstage-y += tsc_freq.c
postcar-y += tsc_freq.c
smm-y += tsc_freq.c
+romstage-y += spi.c
+postcar-y += spi.c
ramstage-y += spi.c
smm-y += spi.c
ramstage-y += chip.c
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 6b466c6..e479a3c 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -15,10 +15,12 @@
romstage-y += memmap.c
romstage-y += pmutil.c
romstage-y += smbus.c
+romstage-y += spi.c
romstage-y += tsc_freq.c

postcar-y += memmap.c
postcar-y += iosf.c
+postcar-y += spi.c
postcar-y += tsc_freq.c

ramstage-y += acpi.c
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 40017eb..a79fa46 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -39,6 +39,9 @@
romstage-y += memmap.c
postcar-y += memmap.c
ramstage-y += minihd.c
+bootblock-y += monotonic_timer.c
+romstage-y += monotonic_timer.c
+postcar-y += monotonic_timer.c
ramstage-y += monotonic_timer.c
smm-y += monotonic_timer.c
ramstage-y += pch.c
@@ -60,6 +63,9 @@
ramstage-y += smi.c
smm-y += smihandler.c
ramstage-y += smmrelocate.c
+bootblock-y += spi.c
+romstage-y += spi.c
+postcar-y += spi.c
ramstage-y += spi.c
smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
ramstage-y += stage_cache.c

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5
Gerrit-Change-Number: 32878
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com>
Gerrit-MessageType: newchange